#include <string>
#include "base/inet.hh"
-#include "base/statistics.hh"
+#include "dev/etherdevice.hh"
#include "dev/etherint.hh"
#include "dev/etherpkt.hh"
#include "dev/i8254xGBe_defs.hh"
#include "dev/pcidev.hh"
#include "dev/pktfifo.hh"
+#include "params/IGbE.hh"
#include "sim/eventq.hh"
class IGbEInt;
-class IGbE : public PciDev
+class IGbE : public EtherDevice
{
private:
IGbEInt *etherInt;
uint8_t eeOpcode, eeAddr;
uint16_t flash[iGbReg::EEPROM_SIZE];
+ // The drain event if we have one
+ Event *drainEvent;
+
// cached parameters from params struct
- Tick tickRate;
bool useFlowControl;
// packet fifos
// Should to Rx/Tx State machine tick?
bool rxTick;
bool txTick;
+ bool txFifoTick;
+
+ bool rxDmaPacket;
+
+ // Delays in managaging descriptors
+ Tick fetchDelay, wbDelay;
+ Tick fetchCompDelay, wbCompDelay;
+ Tick rxWriteDelay, txReadDelay;
// Event and function to deal with RDTR timer expiring
- void rdtrProcess() { postInterrupt(iGbReg::IT_RXDMT, true); }
+ void rdtrProcess() {
+ rxDescCache.writeback(0);
+ DPRINTF(EthernetIntr, "Posting RXT interrupt because RDTR timer expired\n");
+ postInterrupt(iGbReg::IT_RXT);
+ }
+
//friend class EventWrapper<IGbE, &IGbE::rdtrProcess>;
EventWrapper<IGbE, &IGbE::rdtrProcess> rdtrEvent;
// Event and function to deal with RADV timer expiring
- void radvProcess() { postInterrupt(iGbReg::IT_RXDMT, true); }
+ void radvProcess() {
+ rxDescCache.writeback(0);
+ DPRINTF(EthernetIntr, "Posting RXT interrupt because RADV timer expired\n");
+ postInterrupt(iGbReg::IT_RXT);
+ }
+
//friend class EventWrapper<IGbE, &IGbE::radvProcess>;
EventWrapper<IGbE, &IGbE::radvProcess> radvEvent;
// Event and function to deal with TADV timer expiring
- void tadvProcess() { postInterrupt(iGbReg::IT_TXDW, true); }
+ void tadvProcess() {
+ txDescCache.writeback(0);
+ DPRINTF(EthernetIntr, "Posting TXDW interrupt because TADV timer expired\n");
+ postInterrupt(iGbReg::IT_TXDW);
+ }
+
//friend class EventWrapper<IGbE, &IGbE::tadvProcess>;
EventWrapper<IGbE, &IGbE::tadvProcess> tadvEvent;
// Event and function to deal with TIDV timer expiring
- void tidvProcess() { postInterrupt(iGbReg::IT_TXDW, true); };
+ void tidvProcess() {
+ txDescCache.writeback(0);
+ DPRINTF(EthernetIntr, "Posting TXDW interrupt because TIDV timer expired\n");
+ postInterrupt(iGbReg::IT_TXDW);
+ }
//friend class EventWrapper<IGbE, &IGbE::tidvProcess>;
EventWrapper<IGbE, &IGbE::tidvProcess> tidvEvent;
EventWrapper<IGbE, &IGbE::tick> tickEvent;
+ uint64_t macAddr;
+
void rxStateMachine();
void txStateMachine();
void txWire();
/** Send an interrupt to the cpu
*/
+ void delayIntEvent();
void cpuPostInt();
// Event to moderate interrupts
- EventWrapper<IGbE, &IGbE::cpuPostInt> interEvent;
+ EventWrapper<IGbE, &IGbE::delayIntEvent> interEvent;
/** Clear the interupt line to the cpu
*/
Tick intClock() { return Clock::Int::ns * 1024; }
+ /** This function is used to restart the clock so it can handle things like
+ * draining and resume in one place. */
+ void restartClock();
+
+ /** Check if all the draining things that need to occur have occured and
+ * handle the drain event if so.
+ */
+ void checkDrain();
+
template<class T>
class DescCache
{
virtual long descLen() const = 0;
virtual void updateHead(long h) = 0;
virtual void enableSm() = 0;
+ virtual void intAfterWb() const {}
+ virtual void fetchAfterWb() = 0;
std::deque<T*> usedCache;
std::deque<T*> unusedCache;
public:
DescCache(IGbE *i, const std::string n, int s)
: igbe(i), _name(n), cachePnt(0), size(s), curFetching(0), wbOut(0),
- pktPtr(NULL), fetchEvent(this), wbEvent(this)
+ pktPtr(NULL), wbDelayEvent(this), fetchDelayEvent(this),
+ fetchEvent(this), wbEvent(this)
{
fetchBuf = new T[size];
wbBuf = new T[size];
*/
void areaChanged()
{
- if (usedCache.size() > 0 || unusedCache.size() > 0)
+ if (usedCache.size() > 0 || curFetching || wbOut)
panic("Descriptor Address, Length or Head changed. Bad\n");
+ reset();
+
}
void writeback(Addr aMask)
{
int curHead = descHead();
- int max_to_wb = usedCache.size() + curHead;
-
- DPRINTF(EthernetDesc, "Writing back descriptors head: %d tail: "
- "%d len: %d cachePnt: %d max_to_wb: %d descleft: %d\n",
- curHead, descTail(), descLen(), cachePnt, max_to_wb,
- descLeft());
+ int max_to_wb = usedCache.size();
// Check if this writeback is less restrictive that the previous
// and if so setup another one immediately following it
- if (wbOut && (aMask < wbAlignment)) {
- moreToWb = true;
- wbAlignment = aMask;
+ if (wbOut) {
+ if (aMask < wbAlignment) {
+ moreToWb = true;
+ wbAlignment = aMask;
+ }
DPRINTF(EthernetDesc, "Writing back already in process, returning\n");
return;
}
-
moreToWb = false;
wbAlignment = aMask;
+
+
+ DPRINTF(EthernetDesc, "Writing back descriptors head: %d tail: "
+ "%d len: %d cachePnt: %d max_to_wb: %d descleft: %d\n",
+ curHead, descTail(), descLen(), cachePnt, max_to_wb,
+ descLeft());
- if (max_to_wb > descLen()) {
+ if (max_to_wb + curHead >= descLen()) {
max_to_wb = descLen() - curHead;
moreToWb = true;
// this is by definition aligned correctly
- } else if (aMask != 0) {
+ } else if (wbAlignment != 0) {
// align the wb point to the mask
- max_to_wb = max_to_wb & ~(aMask>>4);
+ max_to_wb = max_to_wb & ~wbAlignment;
}
DPRINTF(EthernetDesc, "Writing back %d descriptors\n", max_to_wb);
- if (max_to_wb <= 0 || wbOut)
+ if (max_to_wb <= 0) {
return;
+ }
- wbOut = max_to_wb - curHead;
+ wbOut = max_to_wb;
- for (int x = 0; x < wbOut; x++)
- memcpy(&wbBuf[x], usedCache[x], sizeof(T));
+ assert(!wbDelayEvent.scheduled());
+ wbDelayEvent.schedule(igbe->wbDelay + curTick);
+ }
+
+ void writeback1()
+ {
+ // If we're draining delay issuing this DMA
+ if (igbe->drainEvent) {
+ wbDelayEvent.schedule(igbe->wbDelay + curTick);
+ return;
+ }
+ DPRINTF(EthernetDesc, "Beining DMA of %d descriptors\n", wbOut);
+
for (int x = 0; x < wbOut; x++) {
assert(usedCache.size());
- delete usedCache[0];
- usedCache.pop_front();
- };
+ memcpy(&wbBuf[x], usedCache[x], sizeof(T));
+ //delete usedCache[0];
+ //usedCache.pop_front();
+ }
- igbe->dmaWrite(descBase() + curHead * sizeof(T), wbOut * sizeof(T),
- &wbEvent, (uint8_t*)wbBuf);
+ assert(wbOut);
+ igbe->dmaWrite(igbe->platform->pciToDma(descBase() + descHead() * sizeof(T)),
+ wbOut * sizeof(T), &wbEvent, (uint8_t*)wbBuf,
+ igbe->wbCompDelay);
}
+ EventWrapper<DescCache, &DescCache::writeback1> wbDelayEvent;
/** Fetch a chunk of descriptors into the descriptor cache.
* Calls fetchComplete when the memory system returns the data
*/
+
void fetchDescriptors()
{
- size_t max_to_fetch = cachePnt - descTail();
- if (max_to_fetch < 0)
+ size_t max_to_fetch;
+
+ if (curFetching) {
+ DPRINTF(EthernetDesc, "Currently fetching %d descriptors, returning\n", curFetching);
+ return;
+ }
+
+ if (descTail() >= cachePnt)
+ max_to_fetch = descTail() - cachePnt;
+ else
max_to_fetch = descLen() - cachePnt;
- max_to_fetch = std::min(max_to_fetch, (size - usedCache.size() -
- unusedCache.size()));
+ size_t free_cache = size - usedCache.size() - unusedCache.size();
+
+ max_to_fetch = std::min(max_to_fetch, free_cache);
+
DPRINTF(EthernetDesc, "Fetching descriptors head: %d tail: "
- "%d len: %d cachePnt: %d max_to_wb: %d descleft: %d\n",
+ "%d len: %d cachePnt: %d max_to_fetch: %d descleft: %d\n",
descHead(), descTail(), descLen(), cachePnt,
max_to_fetch, descLeft());
// Nothing to do
- if (max_to_fetch == 0 || curFetching)
+ if (max_to_fetch == 0)
return;
-
+
// So we don't have two descriptor fetches going on at once
curFetching = max_to_fetch;
- igbe->dmaRead(descBase() + cachePnt * sizeof(T),
- curFetching * sizeof(T), &fetchEvent, (uint8_t*)fetchBuf);
+ assert(!fetchDelayEvent.scheduled());
+ fetchDelayEvent.schedule(igbe->fetchDelay + curTick);
+ }
+
+ void fetchDescriptors1()
+ {
+ // If we're draining delay issuing this DMA
+ if (igbe->drainEvent) {
+ fetchDelayEvent.schedule(igbe->fetchDelay + curTick);
+ return;
+ }
+
+ DPRINTF(EthernetDesc, "Fetching descriptors at %#x (%#x), size: %#x\n",
+ descBase() + cachePnt * sizeof(T),
+ igbe->platform->pciToDma(descBase() + cachePnt * sizeof(T)),
+ curFetching * sizeof(T));
+ assert(curFetching);
+ igbe->dmaRead(igbe->platform->pciToDma(descBase() + cachePnt * sizeof(T)),
+ curFetching * sizeof(T), &fetchEvent, (uint8_t*)fetchBuf,
+ igbe->fetchCompDelay);
}
+ EventWrapper<DescCache, &DescCache::fetchDescriptors1> fetchDelayEvent;
/** Called by event when dma to read descriptors is completed
*/
unusedCache.push_back(newDesc);
}
+
#ifndef NDEBUG
int oldCp = cachePnt;
#endif
cachePnt += curFetching;
- if (cachePnt > descLen())
- cachePnt -= descLen();
+ assert(cachePnt <= descLen());
+ if (cachePnt == descLen())
+ cachePnt = 0;
+
+ curFetching = 0;
DPRINTF(EthernetDesc, "Fetching complete cachePnt %d -> %d\n",
oldCp, cachePnt);
enableSm();
-
+ igbe->checkDrain();
}
EventWrapper<DescCache, &DescCache::fetchComplete> fetchEvent;
*/
void wbComplete()
{
+
long curHead = descHead();
#ifndef NDEBUG
long oldHead = curHead;
#endif
+
+ for (int x = 0; x < wbOut; x++) {
+ assert(usedCache.size());
+ delete usedCache[0];
+ usedCache.pop_front();
+ }
curHead += wbOut;
wbOut = 0;
- if (curHead > descLen())
- curHead = 0;
+ if (curHead >= descLen())
+ curHead -= descLen();
// Update the head
updateHead(curHead);
- DPRINTF(EthernetDesc, "Writeback complete cachePnt %d -> %d\n",
+ DPRINTF(EthernetDesc, "Writeback complete curHead %d -> %d\n",
oldHead, curHead);
// If we still have more to wb, call wb now
+ intAfterWb();
if (moreToWb) {
+ moreToWb = false;
DPRINTF(EthernetDesc, "Writeback has more todo\n");
writeback(wbAlignment);
}
+
+ if (!wbOut) {
+ igbe->checkDrain();
+ }
+ fetchAfterWb();
}
if (cachePnt - descTail() >= 0)
left += (cachePnt - descTail());
else
- left += (descLen() - cachePnt);
+ left += (descTail() - cachePnt);
return left;
}
usedCache.clear();
unusedCache.clear();
+
+ cachePnt = 0;
+
+ }
+
+ virtual void serialize(std::ostream &os)
+ {
+ SERIALIZE_SCALAR(cachePnt);
+ SERIALIZE_SCALAR(curFetching);
+ SERIALIZE_SCALAR(wbOut);
+ SERIALIZE_SCALAR(moreToWb);
+ SERIALIZE_SCALAR(wbAlignment);
+
+ int usedCacheSize = usedCache.size();
+ SERIALIZE_SCALAR(usedCacheSize);
+ for(int x = 0; x < usedCacheSize; x++) {
+ arrayParamOut(os, csprintf("usedCache_%d", x),
+ (uint8_t*)usedCache[x],sizeof(T));
+ }
+
+ int unusedCacheSize = unusedCache.size();
+ SERIALIZE_SCALAR(unusedCacheSize);
+ for(int x = 0; x < unusedCacheSize; x++) {
+ arrayParamOut(os, csprintf("unusedCache_%d", x),
+ (uint8_t*)unusedCache[x],sizeof(T));
+ }
+
+ Tick fetch_delay = 0, wb_delay = 0;
+ if (fetchDelayEvent.scheduled())
+ fetch_delay = fetchDelayEvent.when();
+ SERIALIZE_SCALAR(fetch_delay);
+ if (wbDelayEvent.scheduled())
+ wb_delay = wbDelayEvent.when();
+ SERIALIZE_SCALAR(wb_delay);
+
+
+ }
+
+ virtual void unserialize(Checkpoint *cp, const std::string §ion)
+ {
+ UNSERIALIZE_SCALAR(cachePnt);
+ UNSERIALIZE_SCALAR(curFetching);
+ UNSERIALIZE_SCALAR(wbOut);
+ UNSERIALIZE_SCALAR(moreToWb);
+ UNSERIALIZE_SCALAR(wbAlignment);
+
+ int usedCacheSize;
+ UNSERIALIZE_SCALAR(usedCacheSize);
+ T *temp;
+ for(int x = 0; x < usedCacheSize; x++) {
+ temp = new T;
+ arrayParamIn(cp, section, csprintf("usedCache_%d", x),
+ (uint8_t*)temp,sizeof(T));
+ usedCache.push_back(temp);
+ }
+
+ int unusedCacheSize;
+ UNSERIALIZE_SCALAR(unusedCacheSize);
+ for(int x = 0; x < unusedCacheSize; x++) {
+ temp = new T;
+ arrayParamIn(cp, section, csprintf("unusedCache_%d", x),
+ (uint8_t*)temp,sizeof(T));
+ unusedCache.push_back(temp);
+ }
+ Tick fetch_delay = 0, wb_delay = 0;
+ UNSERIALIZE_SCALAR(fetch_delay);
+ UNSERIALIZE_SCALAR(wb_delay);
+ if (fetch_delay)
+ fetchDelayEvent.schedule(fetch_delay);
+ if (wb_delay)
+ wbDelayEvent.schedule(wb_delay);
+
+
+ }
+ virtual bool hasOutstandingEvents() {
+ return wbEvent.scheduled() || fetchEvent.scheduled();
}
};
virtual long descTail() const { return igbe->regs.rdt(); }
virtual void updateHead(long h) { igbe->regs.rdh(h); }
virtual void enableSm();
+ virtual void fetchAfterWb() {
+ if (!igbe->rxTick && igbe->getState() == SimObject::Running)
+ fetchDescriptors();
+ }
bool pktDone;
* @param packet ethernet packet to write
* @return if the packet could be written (there was a free descriptor)
*/
- bool writePacket(EthPacketPtr packet);
+ void writePacket(EthPacketPtr packet);
/** Called by event when dma to write packet is completed
*/
void pktComplete();
EventWrapper<RxDescCache, &RxDescCache::pktComplete> pktEvent;
+ virtual bool hasOutstandingEvents();
+
+ virtual void serialize(std::ostream &os);
+ virtual void unserialize(Checkpoint *cp, const std::string §ion);
};
friend class RxDescCache;
virtual long descLen() const { return igbe->regs.tdlen() >> 4; }
virtual void updateHead(long h) { igbe->regs.tdh(h); }
virtual void enableSm();
+ virtual void intAfterWb() const { igbe->postInterrupt(iGbReg::IT_TXDW); }
+ virtual void fetchAfterWb() {
+ if (!igbe->txTick && igbe->getState() == SimObject::Running)
+ fetchDescriptors();
+ }
bool pktDone;
bool isTcp;
bool pktWaiting;
+ bool pktMultiDesc;
public:
TxDescCache(IGbE *i, std::string n, int s);
*/
bool packetWaiting() { return pktWaiting; }
+ /** Ask if this packet is composed of multiple descriptors
+ * so even if we've got data, we need to wait for more before
+ * we can send it out.
+ * @return packet can't be sent out because it's a multi-descriptor
+ * packet
+ */
+ bool packetMultiDesc() { return pktMultiDesc;}
+
/** Called by event when dma to write packet is completed
*/
void pktComplete();
EventWrapper<TxDescCache, &TxDescCache::pktComplete> pktEvent;
+ virtual bool hasOutstandingEvents();
+
+ virtual void serialize(std::ostream &os);
+ virtual void unserialize(Checkpoint *cp, const std::string §ion);
+
};
friend class TxDescCache;
TxDescCache txDescCache;
public:
- struct Params : public PciDev::Params
+ typedef IGbEParams Params;
+ const Params *
+ params() const
{
- bool use_flow_control;
- int rx_fifo_size;
- int tx_fifo_size;
- int rx_desc_cache_size;
- int tx_desc_cache_size;
- Tick clock;
- };
+ return dynamic_cast<const Params *>(_params);
+ }
+ IGbE(const Params *params);
+ ~IGbE() {}
- IGbE(Params *params);
- ~IGbE() {;}
+ virtual EtherInt *getEthPort(const std::string &if_name, int idx);
Tick clock;
- inline Tick cycles(int numCycles) const { return numCycles * clock; }
+ Tick lastInterrupt;
+ inline Tick ticks(int numCycles) const { return numCycles * clock; }
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
bool ethRxPkt(EthPacketPtr packet);
void ethTxDone();
- void setEthInt(IGbEInt *i) { assert(!etherInt); etherInt = i; }
-
-
- const Params *params() const {return (const Params *)_params; }
-
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string §ion);
-
+ virtual unsigned int drain(Event *de);
+ virtual void resume();
};
public:
IGbEInt(const std::string &name, IGbE *d)
: EtherInt(name), dev(d)
- { dev->setEthInt(this); }
+ { }
virtual bool recvPacket(EthPacketPtr pkt) { return dev->ethRxPkt(pkt); }
virtual void sendDone() { dev->ethTxDone(); }
projects / gem5.git / blobdiff