#include "base/trace.hh"
#include "cpu/intr_control.hh"
+#include "debug/IdeCtrl.hh"
#include "dev/ide_ctrl.hh"
#include "dev/ide_disk.hh"
#include "mem/packet.hh"
primary.select(false);
secondary.select(false);
- if ((BARAddrs[0] & ~BAR_IO_MASK) != 0){
+ if ((BARAddrs[0] & ~BAR_IO_MASK) && (!legacyIO[0] || ioShift)) {
primary.cmdAddr = BARAddrs[0]; primary.cmdSize = BARSize[0];
primary.ctrlAddr = BARAddrs[1]; primary.ctrlSize = BARAddrs[1];
}
- if ((BARAddrs[2] & ~BAR_IO_MASK) != 0){
+ if ((BARAddrs[2] & ~BAR_IO_MASK) && (!legacyIO[2] || ioShift)) {
secondary.cmdAddr = BARAddrs[2]; secondary.cmdSize = BARSize[2];
secondary.ctrlAddr = BARAddrs[3]; secondary.ctrlSize = BARAddrs[3];
}
(uint32_t)pkt->get<uint16_t>());
break;
case sizeof(uint32_t):
- panic("No 32bit reads implemented for this device.");
+ if (offset == IDEConfig)
+ pkt->set<uint32_t>(ideConfig);
+ else
+ panic("No 32bit reads implemented for this device.");
DPRINTF(IdeCtrl, "PCI read offset: %#x size: 4 data: %#x\n", offset,
(uint32_t)pkt->get<uint32_t>());
break;
offset, (uint32_t)pkt->get<uint16_t>());
break;
case sizeof(uint32_t):
- panic("Write of unimplemented PCI config. register: %x\n", offset);
+ if (offset == IDEConfig)
+ ideConfig = pkt->get<uint32_t>();
+ else
+ panic("Write of unimplemented PCI config. register: %x\n", offset);
break;
default:
panic("invalid access size(?) for PCI configspace!\n");
break;
case PCI_COMMAND:
+ DPRINTF(IdeCtrl, "Writing to PCI Command val: %#x\n", config.command);
ioEnabled = (config.command & htole(PCI_CMD_IOSE));
bmEnabled = (config.command & htole(PCI_CMD_BME));
break;