#include "dev/platform.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
-#include "sim/builder.hh"
+#include "params/IdeController.hh"
#include "sim/sim_object.hh"
#include "sim/byteswap.hh"
////
Tick
-IdeController::readConfig(Packet *pkt)
+IdeController::readConfig(PacketPtr pkt)
{
int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
- if (offset < PCI_DEVICE_SPECIFIC)
- return PciDev::readConfig(pkt);
+ if (offset < PCI_DEVICE_SPECIFIC) {
+ return PciDev::readConfig(pkt);
+ }
+
assert(offset >= IDE_CTRL_CONF_START && (offset + 1) <= IDE_CTRL_CONF_END);
pkt->allocate();
default:
panic("invalid access size(?) for PCI configspace!\n");
}
- pkt->result = Packet::Success;
+ pkt->makeAtomicResponse();
return configDelay;
-
}
Tick
-IdeController::writeConfig(Packet *pkt)
+IdeController::writeConfig(PacketPtr pkt)
{
int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
if (offset < PCI_DEVICE_SPECIFIC) {
default:
panic("invalid access size(?) for PCI configspace!\n");
}
+ pkt->makeAtomicResponse();
}
/* Trap command register writes and enable IO/BM as appropriate as well as
bm_enabled = false;
break;
}
- pkt->result = Packet::Success;
return configDelay;
}
Tick
-IdeController::read(Packet *pkt)
+IdeController::read(PacketPtr pkt)
{
Addr offset;
IdeChannel channel;
parseAddr(pkt->getAddr(), offset, channel, reg_type);
if (!io_enabled) {
- pkt->result = Packet::Success;
+ pkt->makeAtomicResponse();
return pioDelay;
}
DPRINTF(IdeCtrl, "read from offset: %#x size: %#x data: %#x\n",
offset, pkt->getSize(), pkt->get<uint32_t>());
- pkt->result = Packet::Success;
+ pkt->makeAtomicResponse();
return pioDelay;
}
Tick
-IdeController::write(Packet *pkt)
+IdeController::write(PacketPtr pkt)
{
Addr offset;
IdeChannel channel;
parseAddr(pkt->getAddr(), offset, channel, reg_type);
if (!io_enabled) {
- pkt->result = Packet::Success;
+ pkt->makeAtomicResponse();
DPRINTF(IdeCtrl, "io not enabled\n");
return pioDelay;
}
switch (reg_type) {
case BMI_BLOCK:
if (!bm_enabled) {
- pkt->result = Packet::Success;
+ pkt->makeAtomicResponse();
return pioDelay;
}
offset, pkt->getSize(), pkt->get<uint32_t>());
- pkt->result = Packet::Success;
+ pkt->makeAtomicResponse();
return pioDelay;
}
sizeof(cmd_in_progress) / sizeof(cmd_in_progress[0]));
}
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeController)
-
- SimObjectParam<System *> system;
- SimObjectParam<Platform *> platform;
- SimObjectParam<PciConfigData *> configdata;
- Param<uint32_t> pci_bus;
- Param<uint32_t> pci_dev;
- Param<uint32_t> pci_func;
- Param<Tick> pio_latency;
- Param<Tick> config_latency;
- SimObjectVectorParam<IdeDisk *> disks;
-
-END_DECLARE_SIM_OBJECT_PARAMS(IdeController)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(IdeController)
-
- INIT_PARAM(system, "System pointer"),
- INIT_PARAM(platform, "Platform pointer"),
- INIT_PARAM(configdata, "PCI Config data"),
- INIT_PARAM(pci_bus, "PCI bus ID"),
- INIT_PARAM(pci_dev, "PCI device number"),
- INIT_PARAM(pci_func, "PCI function code"),
- INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
- INIT_PARAM(config_latency, "Number of cycles for a config read or write"),
- INIT_PARAM(disks, "IDE disks attached to this controller")
-
-END_INIT_SIM_OBJECT_PARAMS(IdeController)
-
-CREATE_SIM_OBJECT(IdeController)
+IdeController *
+IdeControllerParams::create()
{
- IdeController::Params *params = new IdeController::Params;
- params->name = getInstanceName();
- params->platform = platform;
- params->system = system;
- params->configData = configdata;
- params->busNum = pci_bus;
- params->deviceNum = pci_dev;
- params->functionNum = pci_func;
- params->pio_delay = pio_latency;
- params->config_delay = config_latency;
- params->disks = disks;
- return new IdeController(params);
+ return new IdeController(this);
}
-
-REGISTER_SIM_OBJECT("IdeController", IdeController)
-
-#endif //DOXYGEN_SHOULD_SKIP_THIS