SimObjects: Clean up handling of C++ namespaces.

[gem5.git] / src / dev / ide_disk.cc

diff --git a/src/dev/ide_disk.cc b/src/dev/ide_disk.cc
index 9fa0cedded139a6f166e8befb4cb1e6a9b34d8a8..9022cf087ef2255e7cda9f97eebf79eb3fca7266 100644 (file)
--- a/src/dev/ide_disk.cc
+++ b/src/dev/ide_disk.cc
@@ -38,31 +38,27 @@
 #include <deque>
 #include <string>
 
+#include "arch/isa_traits.hh"
 #include "base/chunk_generator.hh"
 #include "base/cprintf.hh" // csprintf
 #include "base/trace.hh"
 #include "dev/disk_image.hh"
-#include "dev/ide_disk.hh"
 #include "dev/ide_ctrl.hh"
-#include "dev/alpha/tsunami.hh"
-#include "dev/alpha/tsunami_pchip.hh"
-#include "sim/builder.hh"
-#include "sim/sim_object.hh"
+#include "dev/ide_disk.hh"
 #include "sim/core.hh"
-#include "arch/isa_traits.hh"
+#include "sim/sim_object.hh"
 
 using namespace std;
 using namespace TheISA;
 
-IdeDisk::IdeDisk(const string &name, DiskImage *img,
-                 int id, Tick delay)
-    : SimObject(name), ctrl(NULL), image(img), diskDelay(delay),
+IdeDisk::IdeDisk(const Params *p)
+    : SimObject(p), ctrl(NULL), image(p->image), diskDelay(p->delay),
       dmaTransferEvent(this), dmaReadCG(NULL), dmaReadWaitEvent(this),
       dmaWriteCG(NULL), dmaWriteWaitEvent(this), dmaPrdReadEvent(this),
       dmaReadEvent(this), dmaWriteEvent(this)
 {
     // Reset the device state
-    reset(id);
+    reset(p->driveID);
 
     // fill out the drive ID structure
     memset(&driveID, 0, sizeof(struct ataparams));
@@ -319,7 +315,7 @@ IdeDisk::doDmaTransfer()
               dmaState, devState);
 
     if (ctrl->dmaPending() || ctrl->getState() != SimObject::Running) {
-        dmaTransferEvent.schedule(curTick + DMA_BACKOFF_PERIOD);
+        schedule(dmaTransferEvent, curTick + DMA_BACKOFF_PERIOD);
         return;
     } else
         ctrl->dmaRead(curPrdAddr, sizeof(PrdEntry_t), &dmaPrdReadEvent,
@@ -353,7 +349,7 @@ IdeDisk::doDmaDataRead()
     DPRINTF(IdeDisk, "doDmaRead, diskDelay: %d totalDiskDelay: %d\n",
             diskDelay, totalDiskDelay);
 
-    dmaReadWaitEvent.schedule(curTick + totalDiskDelay);
+    schedule(dmaReadWaitEvent, curTick + totalDiskDelay);
 }
 
 void
@@ -399,7 +395,7 @@ IdeDisk::doDmaRead()
 
     }
     if (ctrl->dmaPending() || ctrl->getState() != SimObject::Running) {
-        dmaReadWaitEvent.schedule(curTick + DMA_BACKOFF_PERIOD);
+        schedule(dmaReadWaitEvent, curTick + DMA_BACKOFF_PERIOD);
         return;
     } else if (!dmaReadCG->done()) {
         assert(dmaReadCG->complete() < MAX_DMA_SIZE);
@@ -461,7 +457,7 @@ IdeDisk::doDmaDataWrite()
         cmdBytesLeft -= SectorSize;
     }
 
-    dmaWriteWaitEvent.schedule(curTick + totalDiskDelay);
+    schedule(dmaWriteWaitEvent, curTick + totalDiskDelay);
 }
 
 void
@@ -474,7 +470,7 @@ IdeDisk::doDmaWrite()
                 curPrd.getByteCount(), TheISA::PageBytes);
     }
     if (ctrl->dmaPending() || ctrl->getState() != SimObject::Running) {
-        dmaWriteWaitEvent.schedule(curTick + DMA_BACKOFF_PERIOD);
+        schedule(dmaWriteWaitEvent, curTick + DMA_BACKOFF_PERIOD);
         return;
     } else if (!dmaWriteCG->done()) {
         assert(dmaWriteCG->complete() < MAX_DMA_SIZE);
@@ -549,7 +545,7 @@ IdeDisk::startDma(const uint32_t &prdTableBase)
     dmaState = Dma_Transfer;
 
     // schedule dma transfer (doDmaTransfer)
-    dmaTransferEvent.schedule(curTick + 1);
+    schedule(dmaTransferEvent, curTick + 1);
 }
 
 void
@@ -1077,12 +1073,12 @@ IdeDisk::unserialize(Checkpoint *cp, const string &section)
 
     switch (event) {
       case None : break;
-      case Transfer : dmaTransferEvent.schedule(reschedule); break;
-      case ReadWait : dmaReadWaitEvent.schedule(reschedule); break;
-      case WriteWait : dmaWriteWaitEvent.schedule(reschedule); break;
-      case PrdRead : dmaPrdReadEvent.schedule(reschedule); break;
-      case DmaRead : dmaReadEvent.schedule(reschedule); break;
-      case DmaWrite : dmaWriteEvent.schedule(reschedule); break;
+      case Transfer : schedule(dmaTransferEvent, reschedule); break;
+      case ReadWait : schedule(dmaReadWaitEvent, reschedule); break;
+      case WriteWait : schedule(dmaWriteWaitEvent, reschedule); break;
+      case PrdRead : schedule(dmaPrdReadEvent, reschedule); break;
+      case DmaRead : schedule(dmaReadEvent, reschedule); break;
+      case DmaWrite : schedule(dmaWriteEvent, reschedule); break;
     }
 
     // Unserialize device registers
@@ -1116,32 +1112,8 @@ IdeDisk::unserialize(Checkpoint *cp, const string &section)
     UNSERIALIZE_ARRAY(dataBuffer, MAX_DMA_SIZE);
 }
 
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-enum DriveID { master, slave };
-static const char *DriveID_strings[] = { "master", "slave" };
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeDisk)
-
-    SimObjectParam<DiskImage *> image;
-    SimpleEnumParam<DriveID> driveID;
-    Param<int> delay;
-
-END_DECLARE_SIM_OBJECT_PARAMS(IdeDisk)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(IdeDisk)
-
-    INIT_PARAM(image, "Disk image"),
-    INIT_ENUM_PARAM(driveID, "Drive ID (0=master 1=slave)", DriveID_strings),
-    INIT_PARAM_DFLT(delay, "Fixed disk delay in microseconds", 1)
-
-END_INIT_SIM_OBJECT_PARAMS(IdeDisk)
-
-
-CREATE_SIM_OBJECT(IdeDisk)
+IdeDisk *
+IdeDiskParams::create()
 {
-    return new IdeDisk(getInstanceName(), image, driveID, delay);
+    return new IdeDisk(this);
 }
-
-REGISTER_SIM_OBJECT("IdeDisk", IdeDisk)
-
-#endif //DOXYGEN_SHOULD_SKIP_THIS