inorder: squash on memory stall

[gem5.git] / src / dev / ide_disk.hh

diff --git a/src/dev/ide_disk.hh b/src/dev/ide_disk.hh
index 5379e5e73ffbfab9f1aa0da6f2b0264cab980692..1b455e8ad3ba2f1f1718b9ef72ed527106ec1104 100644 (file)
--- a/src/dev/ide_disk.hh
+++ b/src/dev/ide_disk.hh
@@ -24,6 +24,8 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andrew Schultz
  */
 
 /** @file
@@ -40,6 +42,10 @@
 #include "dev/ide_wdcreg.h"
 #include "dev/io_device.hh"
 #include "sim/eventq.hh"
+#include "params/IdeDisk.hh"
+
+
+class ChunkGenerator;
 
 #define DMA_BACKOFF_PERIOD 200
 
@@ -232,22 +238,20 @@ class IdeDisk : public SimObject
     /** Interrupt pending */
     bool intrPending;
 
-    Stats::Scalar<> dmaReadFullPages;
-    Stats::Scalar<> dmaReadBytes;
-    Stats::Scalar<> dmaReadTxs;
-    Stats::Scalar<> dmaWriteFullPages;
-    Stats::Scalar<> dmaWriteBytes;
-    Stats::Scalar<> dmaWriteTxs;
+    Stats::Scalar dmaReadFullPages;
+    Stats::Scalar dmaReadBytes;
+    Stats::Scalar dmaReadTxs;
+    Stats::Scalar dmaWriteFullPages;
+    Stats::Scalar dmaWriteBytes;
+    Stats::Scalar dmaWriteTxs;
+    Stats::Formula rdBandwidth;
+    Stats::Formula wrBandwidth;
+    Stats::Formula totBandwidth;
+    Stats::Formula totBytes;
 
   public:
-    /**
-     * Create and initialize this Disk.
-     * @param name The name of this disk.
-     * @param img The disk image of this disk.
-     * @param id The disk ID (master=0/slave=1)
-     * @param disk_delay The disk delay in milliseconds
-     */
-    IdeDisk(const std::string &name, DiskImage *img, int id, Tick disk_delay);
+    typedef IdeDiskParams Params;
+    IdeDisk(const Params *p);
 
     /**
      * Delete the data buffer.
@@ -274,8 +278,10 @@ class IdeDisk : public SimObject
     }
 
     // Device register read/write
-    void read(const Addr &offset, IdeRegType regtype, uint8_t *data);
-    void write(const Addr &offset, IdeRegType regtype, const uint8_t *data);
+    void readCommand(const Addr offset, int size, uint8_t *data);
+    void readControl(const Addr offset, int size, uint8_t *data);
+    void writeCommand(const Addr offset, int size, const uint8_t *data);
+    void writeControl(const Addr offset, int size, const uint8_t *data);
 
     // Start/abort functions
     void startDma(const uint32_t &prdTableBase);