*/
#include "base/trace.hh"
+#include "debug/IsaFake.hh"
#include "dev/isa_fake.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
Tick
IsaFake::read(PacketPtr pkt)
{
+ pkt->allocate();
+ pkt->makeAtomicResponse();
if (params()->warn_access != "")
warn("Device %s accessed by read to address %#x size=%d\n",
name(), pkt->getAddr(), pkt->getSize());
if (params()->ret_bad_addr) {
- DPRINTF(Tsunami, "read to bad address va=%#x size=%d\n",
+ DPRINTF(IsaFake, "read to bad address va=%#x size=%d\n",
pkt->getAddr(), pkt->getSize());
pkt->setBadAddress();
} else {
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
- DPRINTF(Tsunami, "read va=%#x size=%d\n",
+ DPRINTF(IsaFake, "read va=%#x size=%d\n",
pkt->getAddr(), pkt->getSize());
switch (pkt->getSize()) {
case sizeof(uint64_t):
pkt->set(retData8);
break;
default:
- panic("invalid access size!\n");
+ if (params()->fake_mem)
+ std::memset(pkt->getPtr<uint8_t>(), 0, pkt->getSize());
+ else
+ panic("invalid access size! Device being accessed by cache?\n");
}
- pkt->makeAtomicResponse();
}
return pioDelay;
}
Tick
IsaFake::write(PacketPtr pkt)
{
+ pkt->makeAtomicResponse();
if (params()->warn_access != "") {
uint64_t data;
switch (pkt->getSize()) {
name(), pkt->getAddr(), pkt->getSize(), data);
}
if (params()->ret_bad_addr) {
- DPRINTF(Tsunami, "write to bad address va=%#x size=%d \n",
+ DPRINTF(IsaFake, "write to bad address va=%#x size=%d \n",
pkt->getAddr(), pkt->getSize());
pkt->setBadAddress();
} else {
- DPRINTF(Tsunami, "write - va=%#x size=%d \n",
+ DPRINTF(IsaFake, "write - va=%#x size=%d \n",
pkt->getAddr(), pkt->getSize());
if (params()->update_data) {
panic("invalid access size!\n");
}
}
- pkt->makeAtomicResponse();
}
return pioDelay;
}