*/
#include <sys/time.h>
-#include <time.h>
+#include <ctime>
#include <string>
#include "base/bitfield.hh"
#include "base/time.hh"
#include "base/trace.hh"
+#include "debug/MC146818.hh"
#include "dev/mc146818.hh"
#include "dev/rtcreg.h"
// Datasheet says 1 is sunday
wday = time.tm_wday + 1;
- if (!(stat_regB & RTCB_BIN)) {
+ if (!stat_regB.dm) {
// The datasheet says that the year field can be either BCD or
// years since 1900. Linux seems to be happy with years since
// 1900.
: EventManager(em), _name(n), event(this, frequency), tickEvent(this)
{
memset(clock_data, 0, sizeof(clock_data));
- stat_regA = RTCA_32768HZ | RTCA_1024HZ;
- stat_regB = RTCB_PRDC_IE | RTCB_24HR;
- if (!bcd)
- stat_regB |= RTCB_BIN;
+
+ stat_regA = 0;
+ stat_regA.dv = RTCA_DV_32768HZ;
+ stat_regA.rs = RTCA_RS_1024HZ;
+
+ stat_regB = 0;
+ stat_regB.pie = 1;
+ stat_regB.format24h = 1;
+ stat_regB.dm = bcd ? 0 : 1;
setTime(time);
DPRINTFN("Real-time clock set to %s", asctime(&time));
deschedule(event);
}
+bool
+MC146818::rega_dv_disabled(const RtcRegA ®)
+{
+ return reg.dv == RTCA_DV_DISABLED0 ||
+ reg.dv == RTCA_DV_DISABLED1;
+}
+
void
MC146818::writeData(const uint8_t addr, const uint8_t data)
{
+ bool panic_unsupported(false);
+
if (addr < RTC_STAT_REGA) {
clock_data[addr] = data;
curTime.tm_sec = unbcdize(sec);
curTime.tm_wday = unbcdize(wday) - 1;
} else {
switch (addr) {
- case RTC_STAT_REGA:
- // The "update in progress" bit is read only.
- if ((data & ~RTCA_UIP) != (RTCA_32768HZ | RTCA_1024HZ))
- panic("Unimplemented RTC register A value write!\n");
- replaceBits(stat_regA, data, 6, 0);
- break;
+ case RTC_STAT_REGA: {
+ RtcRegA old_rega(stat_regA);
+ stat_regA = data;
+ // The "update in progress" bit is read only.
+ stat_regA.uip = old_rega;
+
+ if (!rega_dv_disabled(stat_regA) &&
+ stat_regA.dv != RTCA_DV_32768HZ) {
+ inform("RTC: Unimplemented divider configuration: %i\n",
+ stat_regA.dv);
+ panic_unsupported = true;
+ }
+
+ if (stat_regA.rs != RTCA_RS_1024HZ) {
+ inform("RTC: Unimplemented interrupt rate: %i\n",
+ stat_regA.rs);
+ panic_unsupported = true;
+ }
+
+ if (rega_dv_disabled(stat_regA)) {
+ // The divider is disabled, make sure that we don't
+ // schedule any ticks.
+ if (tickEvent.scheduled())
+ deschedule(tickEvent);
+ } else if (rega_dv_disabled(old_rega)) {
+ // According to the specification, the next tick
+ // happens after 0.5s when the divider chain goes
+ // from reset to active. So, we simply schedule the
+ // tick after 0.5s.
+ assert(!tickEvent.scheduled());
+ schedule(tickEvent, curTick() + SimClock::Int::s / 2);
+ }
+ } break;
case RTC_STAT_REGB:
- if ((data & ~(RTCB_PRDC_IE | RTCB_SQWE)) != RTCB_24HR)
- panic("Write to RTC reg B bits that are not implemented!\n");
+ stat_regB = data;
+ if (stat_regB.aie || stat_regB.uie) {
+ inform("RTC: Unimplemented interrupt configuration: %s %s\n",
+ stat_regB.aie ? "alarm" : "",
+ stat_regB.uie ? "update" : "");
+ panic_unsupported = true;
+ }
+
+ if (stat_regB.dm) {
+ inform("RTC: The binary interface is not fully implemented.\n");
+ panic_unsupported = true;
+ }
- if (data & RTCB_PRDC_IE) {
+ if (!stat_regB.format24h) {
+ inform("RTC: The 12h time format not supported.\n");
+ panic_unsupported = true;
+ }
+
+ if (stat_regB.dse) {
+ inform("RTC: Automatic daylight saving time not supported.\n");
+ panic_unsupported = true;
+ }
+
+ if (stat_regB.pie) {
if (!event.scheduled())
event.scheduleIntr();
} else {
if (event.scheduled())
deschedule(event);
}
- stat_regB = data;
break;
case RTC_STAT_REGC:
case RTC_STAT_REGD:
break;
}
}
+
+ if (panic_unsupported)
+ panic("Unimplemented RTC configuration!\n");
+
}
uint8_t
switch (addr) {
case RTC_STAT_REGA:
// toggle UIP bit for linux
- stat_regA ^= RTCA_UIP;
+ stat_regA.uip = !stat_regA.uip;
return stat_regA;
break;
case RTC_STAT_REGB:
}
}
-static time_t
-mkutctime(struct tm *time)
-{
- time_t ret;
- char *tz;
-
- tz = getenv("TZ");
- setenv("TZ", "", 1);
- tzset();
- ret = mktime(time);
- if (tz)
- setenv("TZ", tz, 1);
- else
- unsetenv("TZ");
- tzset();
- return ret;
-}
-
void
MC146818::tickClock()
{
- if (stat_regB & RTCB_NO_UPDT)
+ assert(!rega_dv_disabled(stat_regA));
+
+ if (stat_regB.set)
return;
time_t calTime = mkutctime(&curTime);
calTime++;
void
MC146818::serialize(const string &base, ostream &os)
{
+ uint8_t regA_serial(stat_regA);
+ uint8_t regB_serial(stat_regB);
+
arrayParamOut(os, base + ".clock_data", clock_data, sizeof(clock_data));
- paramOut(os, base + ".stat_regA", stat_regA);
- paramOut(os, base + ".stat_regB", stat_regB);
+ paramOut(os, base + ".stat_regA", (uint8_t)regA_serial);
+ paramOut(os, base + ".stat_regB", (uint8_t)regB_serial);
//
// save the timer tick and rtc clock tick values to correctly reschedule
// them during unserialize
//
- Tick rtcTimerInterruptTickOffset = event.when() - curTick;
+ Tick rtcTimerInterruptTickOffset = event.when() - curTick();
SERIALIZE_SCALAR(rtcTimerInterruptTickOffset);
- Tick rtcClockTickOffset = event.when() - curTick;
+ Tick rtcClockTickOffset = tickEvent.when() - curTick();
SERIALIZE_SCALAR(rtcClockTickOffset);
}
MC146818::unserialize(const string &base, Checkpoint *cp,
const string §ion)
{
+ uint8_t tmp8;
+
arrayParamIn(cp, section, base + ".clock_data", clock_data,
sizeof(clock_data));
- paramIn(cp, section, base + ".stat_regA", stat_regA);
- paramIn(cp, section, base + ".stat_regB", stat_regB);
+
+ paramIn(cp, section, base + ".stat_regA", tmp8);
+ stat_regA = tmp8;
+ paramIn(cp, section, base + ".stat_regB", tmp8);
+ stat_regB = tmp8;
//
// properly schedule the timer and rtc clock events
//
Tick rtcTimerInterruptTickOffset;
UNSERIALIZE_SCALAR(rtcTimerInterruptTickOffset);
- reschedule(event, curTick + rtcTimerInterruptTickOffset);
+ reschedule(event, curTick() + rtcTimerInterruptTickOffset);
Tick rtcClockTickOffset;
UNSERIALIZE_SCALAR(rtcClockTickOffset);
- reschedule(tickEvent, curTick + rtcClockTickOffset);
+ reschedule(tickEvent, curTick() + rtcClockTickOffset);
}
MC146818::RTCEvent::RTCEvent(MC146818 * _parent, Tick i)
: parent(_parent), interval(i)
{
DPRINTF(MC146818, "RTC Event Initilizing\n");
- parent->schedule(this, curTick + interval);
+ parent->schedule(this, curTick() + interval);
}
void
MC146818::RTCEvent::scheduleIntr()
{
- parent->schedule(this, curTick + interval);
+ parent->schedule(this, curTick() + interval);
}
void
MC146818::RTCEvent::process()
{
DPRINTF(MC146818, "RTC Timer Interrupt\n");
- parent->schedule(this, curTick + interval);
+ parent->schedule(this, curTick() + interval);
parent->handleEvent();
}
MC146818::RTCTickEvent::process()
{
DPRINTF(MC146818, "RTC clock tick\n");
- parent->schedule(this, curTick + Clock::Int::s);
+ parent->schedule(this, curTick() + SimClock::Int::s);
parent->tickClock();
}
projects / gem5.git / blobdiff