dev-arm: clang compatibility fix, added missing overrides

[gem5.git] / src / dev / mc146818.hh

diff --git a/src/dev/mc146818.hh b/src/dev/mc146818.hh
index e3365890383240223f24ec039b3c9ddf687adc00..741dca33696f621c66d0a1f5a87411b96ce248b5 100644 (file)
--- a/src/dev/mc146818.hh
+++ b/src/dev/mc146818.hh
@@ -33,8 +33,9 @@
 #ifndef __DEV_MC146818_HH__
 #define __DEV_MC146818_HH__
 
-#include "base/range.hh"
-#include "sim/eventq.hh"
+#include "base/bitunion.hh"
+#include "base/logging.hh"
+#include "sim/eventq_impl.hh"
 
 /** Real-Time Clock (MC146818) */
 class MC146818 : public EventManager
@@ -51,6 +52,7 @@ class MC146818 : public EventManager
     {
         MC146818 * parent;
         Tick interval;
+        Tick offset;
 
         RTCEvent(MC146818 * _parent, Tick i);
 
@@ -68,11 +70,11 @@ class MC146818 : public EventManager
     struct RTCTickEvent : public Event
     {
         MC146818 * parent;
+        Tick offset;
 
-        RTCTickEvent(MC146818 * _parent) : parent(_parent)
-        {
-            parent->schedule(this, curTick + Clock::Int::s);
-        }
+        RTCTickEvent(MC146818 * _parent) :
+            parent(_parent), offset(SimClock::Int::s)
+        {}
 
         /** Event process to occur at interrupt*/
         void process();
@@ -113,17 +115,49 @@ class MC146818 : public EventManager
 
     void setTime(const struct tm time);
 
+    BitUnion8(RtcRegA)
+        Bitfield<7> uip;    /// 1 = date and time update in progress
+        Bitfield<6, 4> dv;  /// Divider configuration
+        /** Rate selection
+            0 = Disabled
+            For 32768 Hz time bases:
+              Freq = 32768Hz / 2**(n-1) for n >= 3
+              Freq = 256Hz if n = 1
+              Freq = 128Hz if n = 2
+            Othwerise:
+              Freq = 32768Hz / 2**(n-1)
+        */
+        Bitfield<3, 0> rs;
+    EndBitUnion(RtcRegA)
+
+    /// Is the DV field in regA set to disabled?
+    static inline bool rega_dv_disabled(const RtcRegA &reg);
+
+    BitUnion8(RtcRegB)
+        Bitfield<7> set;       /// stop clock updates
+        Bitfield<6> pie;       /// 1 = enable periodic clock interrupt
+        Bitfield<5> aie;       /// 1 = enable alarm interrupt
+        Bitfield<4> uie;       /// 1 = enable update-ended interrupt
+        Bitfield<3> sqwe;      /// 1 = output sqare wave at SQW pin
+        Bitfield<2> dm;        /// 0 = BCD, 1 = Binary coded time
+        Bitfield<1> format24h; /// 0 = 12 hours, 1 = 24 hours
+        Bitfield<0> dse;       /// USA Daylight Savings Time enable
+    EndBitUnion(RtcRegB)
+
     /** RTC status register A */
-    uint8_t stat_regA;
+    RtcRegA stat_regA;
 
     /** RTC status register B */
-    uint8_t stat_regB;
+    RtcRegB stat_regB;
 
   public:
     MC146818(EventManager *em, const std::string &name, const struct tm time,
             bool bcd, Tick frequency);
     virtual ~MC146818();
 
+    /** Start ticking */
+    virtual void startup();
+
     /** RTC write data */
     void writeData(const uint8_t addr, const uint8_t data);
 
@@ -137,7 +171,7 @@ class MC146818 : public EventManager
       * @param base The base name of the counter object.
       * @param os The stream to serialize to.
       */
-    void serialize(const std::string &base, std::ostream &os);
+    void serialize(const std::string &base, CheckpointOut &cp) const;
 
     /**
      * Reconstruct the state of this object from a checkpoint.
@@ -145,8 +179,7 @@ class MC146818 : public EventManager
      * @param cp The checkpoint use.
      * @param section The section name of this object
      */
-    void unserialize(const std::string &base, Checkpoint *cp,
-                     const std::string &section);
+    void unserialize(const std::string &base, CheckpointIn &cp);
 };
 
 #endif // __DEV_MC146818_HH__