# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Korey Sewell
from m5.params import *
from m5.proxy import *
-from BadDevice import BadDevice
-from Device import BasicPioDevice
-from MipsBackdoor import MipsBackdoor
-from Pci import PciConfigAll
-from Platform import Platform
-from Uart import Uart8250
+from m5.objects.BadDevice import BadDevice
+from m5.objects.Device import BasicPioDevice
+from m5.objects.Platform import Platform
+from m5.objects.Uart import Uart8250
class MaltaCChip(BasicPioDevice):
type = 'MaltaCChip'
+ cxx_header = "dev/mips/malta_cchip.hh"
malta = Param.Malta(Parent.any, "Malta")
class MaltaIO(BasicPioDevice):
type = 'MaltaIO'
- time = Param.UInt64(1136073600,
+ cxx_header = "dev/mips/malta_io.hh"
+ time = Param.Time('01/01/2009',
"System time to use (0 for actual time, default is 1/1/06)")
+ year_is_bcd = Param.Bool(False,
+ "The RTC should interpret the year as a BCD value")
malta = Param.Malta(Parent.any, "Malta")
- frequency = Param.Frequency('1050Hz', "frequency of interrupts")
-
-class MaltaPChip(BasicPioDevice):
- type = 'MaltaPChip'
- malta = Param.Malta(Parent.any, "Malta")
+ frequency = Param.Frequency('1024Hz', "frequency of interrupts")
class Malta(Platform):
type = 'Malta'
+ cxx_header = "dev/mips/malta.hh"
system = Param.System(Parent.any, "system")
cchip = MaltaCChip(pio_addr=0x801a0000000)
io = MaltaIO(pio_addr=0x801fc000000)
uart = Uart8250(pio_addr=0xBFD003F8)
- backdoor = MipsBackdoor(pio_addr=0xBFD00F00, disk=Parent.simple_disk)
# Attach I/O devices to specified bus object. Can't do this
# earlier, since the bus object itself is typically defined at the
# System level.
def attachIO(self, bus):
- self.cchip.pio = bus.port
- self.io.pio = bus.port
- self.uart.pio = bus.port
- self.backdoor.pio = bus.port
+ self.cchip.pio = bus.mem_side_ports
+ self.io.pio = bus.mem_side_ports
+ self.uart.pio = bus.mem_side_ports