stats: update stats for mmap() change.

[gem5.git] / src / dev / mips / Malta.py

diff --git a/src/dev/mips/Malta.py b/src/dev/mips/Malta.py
index d321a6361d4468939ea80a0bac8a8f87b087c59b..920b5fe944929536abba1a1e33c92e4f02f848c2 100755 (executable)
--- a/src/dev/mips/Malta.py
+++ b/src/dev/mips/Malta.py
@@ -28,41 +28,39 @@
 
 from m5.params import *
 from m5.proxy import *
+
+from BadDevice import BadDevice
 from Device import BasicPioDevice
 from Platform import Platform
-from MipsConsole import MipsConsole
 from Uart import Uart8250
-from Pci import PciConfigAll
-from BadDevice import BadDevice
 
 class MaltaCChip(BasicPioDevice):
     type = 'MaltaCChip'
+    cxx_header = "dev/mips/malta_cchip.hh"
     malta = Param.Malta(Parent.any, "Malta")
 
 class MaltaIO(BasicPioDevice):
     type = 'MaltaIO'
-    time = Param.UInt64(1136073600,
+    cxx_header = "dev/mips/malta_io.hh"
+    time = Param.Time('01/01/2009',
         "System time to use (0 for actual time, default is 1/1/06)")
+    year_is_bcd = Param.Bool(False,
+            "The RTC should interpret the year as a BCD value")
     malta = Param.Malta(Parent.any, "Malta")
-    frequency = Param.Frequency('1050Hz', "frequency of interrupts")
-
-class MaltaPChip(BasicPioDevice):
-    type = 'MaltaPChip'
-    malta = Param.Malta(Parent.any, "Malta")
+    frequency = Param.Frequency('1024Hz', "frequency of interrupts")
 
 class Malta(Platform):
     type = 'Malta'
+    cxx_header = "dev/mips/malta.hh"
     system = Param.System(Parent.any, "system")
     cchip = MaltaCChip(pio_addr=0x801a0000000)
     io = MaltaIO(pio_addr=0x801fc000000)
     uart = Uart8250(pio_addr=0xBFD003F8)
-    console = MipsConsole(pio_addr=0xBFD00F00, disk=Parent.simple_disk)
 
     # Attach I/O devices to specified bus object.  Can't do this
     # earlier, since the bus object itself is typically defined at the
     # System level.
     def attachIO(self, bus):
-        self.cchip.pio = bus.port
-        self.io.pio = bus.port
-        self.uart.pio = bus.port
-        self.console.pio = bus.port
+        self.cchip.pio = bus.master
+        self.io.pio = bus.master
+        self.uart.pio = bus.master