#include "base/trace.hh"
#include "dev/pciconfigall.hh"
#include "dev/pcidev.hh"
-#include "dev/tsunamireg.h"
+#include "dev/alpha/tsunamireg.h"
#include "mem/packet.hh"
+#include "mem/packet_access.hh"
#include "sim/builder.hh"
#include "sim/byteswap.hh"
#include "sim/param.hh"
Tick
-PciDev::PciConfigPort::recvAtomic(Packet *pkt)
+PciDev::PciConfigPort::recvAtomic(PacketPtr pkt)
{
assert(pkt->result == Packet::Unknown);
assert(pkt->getAddr() >= configAddr &&
}
Tick
-PciDev::readConfig(Packet *pkt)
+PciDev::readConfig(PacketPtr pkt)
{
int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
if (offset >= PCI_DEVICE_SPECIFIC)
}
Tick
-PciDev::writeConfig(Packet *pkt)
+PciDev::writeConfig(PacketPtr pkt)
{
int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
if (offset >= PCI_DEVICE_SPECIFIC)
UNSERIALIZE_ARRAY(BARAddrs, sizeof(BARAddrs) / sizeof(BARAddrs[0]));
UNSERIALIZE_ARRAY(config.data,
sizeof(config.data) / sizeof(config.data[0]));
+ pioPort->sendStatusChange(Port::RangeChange);
+
}
#ifndef DOXYGEN_SHOULD_SKIP_THIS
{
PciConfigData *data = new PciConfigData(getInstanceName());
- data->config.vendor = htole(VendorID);
- data->config.device = htole(DeviceID);
- data->config.command = htole(Command);
- data->config.status = htole(Status);
- data->config.revision = htole(Revision);
- data->config.progIF = htole(ProgIF);
- data->config.subClassCode = htole(SubClassCode);
- data->config.classCode = htole(ClassCode);
- data->config.cacheLineSize = htole(CacheLineSize);
- data->config.latencyTimer = htole(LatencyTimer);
- data->config.headerType = htole(HeaderType);
- data->config.bist = htole(BIST);
-
- data->config.baseAddr[0] = htole(BAR0);
- data->config.baseAddr[1] = htole(BAR1);
- data->config.baseAddr[2] = htole(BAR2);
- data->config.baseAddr[3] = htole(BAR3);
- data->config.baseAddr[4] = htole(BAR4);
- data->config.baseAddr[5] = htole(BAR5);
- data->config.cardbusCIS = htole(CardbusCIS);
- data->config.subsystemVendorID = htole(SubsystemVendorID);
- data->config.subsystemID = htole(SubsystemVendorID);
- data->config.expansionROM = htole(ExpansionROM);
- data->config.interruptLine = htole(InterruptLine);
- data->config.interruptPin = htole(InterruptPin);
- data->config.minimumGrant = htole(MinimumGrant);
- data->config.maximumLatency = htole(MaximumLatency);
+ data->config.vendor = htole(VendorID.returnValue());
+ data->config.device = htole(DeviceID.returnValue());
+ data->config.command = htole(Command.returnValue());
+ data->config.status = htole(Status.returnValue());
+ data->config.revision = htole(Revision.returnValue());
+ data->config.progIF = htole(ProgIF.returnValue());
+ data->config.subClassCode = htole(SubClassCode.returnValue());
+ data->config.classCode = htole(ClassCode.returnValue());
+ data->config.cacheLineSize = htole(CacheLineSize.returnValue());
+ data->config.latencyTimer = htole(LatencyTimer.returnValue());
+ data->config.headerType = htole(HeaderType.returnValue());
+ data->config.bist = htole(BIST.returnValue());
+
+ data->config.baseAddr[0] = htole(BAR0.returnValue());
+ data->config.baseAddr[1] = htole(BAR1.returnValue());
+ data->config.baseAddr[2] = htole(BAR2.returnValue());
+ data->config.baseAddr[3] = htole(BAR3.returnValue());
+ data->config.baseAddr[4] = htole(BAR4.returnValue());
+ data->config.baseAddr[5] = htole(BAR5.returnValue());
+ data->config.cardbusCIS = htole(CardbusCIS.returnValue());
+ data->config.subsystemVendorID = htole(SubsystemVendorID.returnValue());
+ data->config.subsystemID = htole(SubsystemID.returnValue());
+ data->config.expansionROM = htole(ExpansionROM.returnValue());
+ data->config.interruptLine = htole(InterruptLine.returnValue());
+ data->config.interruptPin = htole(InterruptPin.returnValue());
+ data->config.minimumGrant = htole(MinimumGrant.returnValue());
+ data->config.maximumLatency = htole(MaximumLatency.returnValue());
data->BARSize[0] = BAR0Size;
data->BARSize[1] = BAR1Size;