* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ * Andrew Schultz
+ * Miguel Serrano
*/
/* @file
#include <vector>
#include "base/inifile.hh"
+#include "base/intmath.hh"
#include "base/misc.hh"
-#include "base/str.hh" // for to_number
+#include "base/str.hh"
#include "base/trace.hh"
+#include "debug/PCIDEV.hh"
+#include "dev/alpha/tsunamireg.h"
#include "dev/pciconfigall.hh"
#include "dev/pcidev.hh"
-#include "dev/tsunamireg.h"
#include "mem/packet.hh"
-#include "sim/builder.hh"
+#include "mem/packet_access.hh"
#include "sim/byteswap.hh"
-#include "sim/param.hh"
-#include "sim/root.hh"
+#include "sim/core.hh"
using namespace std;
-PciDev::PciDev(Params *p)
- : DmaDevice(p), plat(p->platform), configData(p->configData),
- pioDelay(p->pio_delay)
-{
- // copy the config data from the PciConfigData object
- if (configData) {
- memcpy(config.data, configData->config.data, sizeof(config.data));
- memcpy(BARSize, configData->BARSize, sizeof(BARSize));
- memcpy(BARAddrs, configData->BARAddrs, sizeof(BARAddrs));
- } else
- panic("NULL pointer to configuration data");
-
- // Setup pointer in config space to point to this entry
- if (p->configSpace->deviceExists(p->deviceNum, p->functionNum))
- panic("Two PCI devices occuping same dev: %#x func: %#x",
- p->deviceNum, p->functionNum);
- else
- p->configSpace->registerDevice(p->deviceNum, p->functionNum, this);
-}
-void
-PciDev::readConfig(int offset, uint8_t *data)
+PciDev::PciConfigPort::PciConfigPort(PciDev *dev, int busid, int devid,
+ int funcid, Platform *p)
+ : SimpleTimingPort(dev->name() + "-pciconf", dev), device(dev),
+ platform(p), busId(busid), deviceId(devid), functionId(funcid)
{
- if (offset >= PCI_DEVICE_SPECIFIC)
- panic("Device specific PCI config space not implemented!\n");
+ configAddr = platform->calcPciConfigAddr(busId, deviceId, functionId);
+}
- *data = config.data[offset];
- DPRINTF(PCIDEV,
- "read device: %#x function: %#x register: %#x 1 bytes: data: %#x\n",
- params()->deviceNum, params()->functionNum, offset, *data);
+Tick
+PciDev::PciConfigPort::recvAtomic(PacketPtr pkt)
+{
+ assert(pkt->getAddr() >= configAddr &&
+ pkt->getAddr() < configAddr + PCI_CONFIG_SIZE);
+ return pkt->isRead() ? device->readConfig(pkt) : device->writeConfig(pkt);
}
void
-PciDev::addressRanges(AddrRangeList &range_list)
+PciDev::PciConfigPort::getDeviceAddressRanges(AddrRangeList &resp,
+ bool &snoop)
{
- int x = 0;
- range_list.clear();
- for (x = 0; x < 6; x++)
- if (BARAddrs[x] != 0)
- range_list.push_back(RangeSize(BARAddrs[x],BARSize[x]));
+ snoop = false;;
+ if (configAddr != ULL(-1))
+ resp.push_back(RangeSize(configAddr, PCI_CONFIG_SIZE+1));
}
-void
-PciDev::readConfig(int offset, uint16_t *data)
-{
- if (offset >= PCI_DEVICE_SPECIFIC)
- panic("Device specific PCI config space not implemented!\n");
- *data = *(uint16_t*)&config.data[offset];
+PciDev::PciDev(const Params *p)
+ : DmaDevice(p), plat(p->platform), pioDelay(p->pio_latency),
+ configDelay(p->config_latency), configPort(NULL)
+{
+ config.vendor = htole(p->VendorID);
+ config.device = htole(p->DeviceID);
+ config.command = htole(p->Command);
+ config.status = htole(p->Status);
+ config.revision = htole(p->Revision);
+ config.progIF = htole(p->ProgIF);
+ config.subClassCode = htole(p->SubClassCode);
+ config.classCode = htole(p->ClassCode);
+ config.cacheLineSize = htole(p->CacheLineSize);
+ config.latencyTimer = htole(p->LatencyTimer);
+ config.headerType = htole(p->HeaderType);
+ config.bist = htole(p->BIST);
+
+ config.baseAddr[0] = htole(p->BAR0);
+ config.baseAddr[1] = htole(p->BAR1);
+ config.baseAddr[2] = htole(p->BAR2);
+ config.baseAddr[3] = htole(p->BAR3);
+ config.baseAddr[4] = htole(p->BAR4);
+ config.baseAddr[5] = htole(p->BAR5);
+ config.cardbusCIS = htole(p->CardbusCIS);
+ config.subsystemVendorID = htole(p->SubsystemVendorID);
+ config.subsystemID = htole(p->SubsystemID);
+ config.expansionROM = htole(p->ExpansionROM);
+ config.reserved0 = 0;
+ config.reserved1 = 0;
+ config.interruptLine = htole(p->InterruptLine);
+ config.interruptPin = htole(p->InterruptPin);
+ config.minimumGrant = htole(p->MinimumGrant);
+ config.maximumLatency = htole(p->MaximumLatency);
+
+ BARSize[0] = p->BAR0Size;
+ BARSize[1] = p->BAR1Size;
+ BARSize[2] = p->BAR2Size;
+ BARSize[3] = p->BAR3Size;
+ BARSize[4] = p->BAR4Size;
+ BARSize[5] = p->BAR5Size;
+
+ legacyIO[0] = p->BAR0LegacyIO;
+ legacyIO[1] = p->BAR1LegacyIO;
+ legacyIO[2] = p->BAR2LegacyIO;
+ legacyIO[3] = p->BAR3LegacyIO;
+ legacyIO[4] = p->BAR4LegacyIO;
+ legacyIO[5] = p->BAR5LegacyIO;
+
+ for (int i = 0; i < 6; ++i) {
+ if (legacyIO[i]) {
+ BARAddrs[i] = platform->calcPciIOAddr(letoh(config.baseAddr[i]));
+ config.baseAddr[i] = 0;
+ } else {
+ BARAddrs[i] = 0;
+ uint32_t barsize = BARSize[i];
+ if (barsize != 0 && !isPowerOf2(barsize)) {
+ fatal("BAR %d size %d is not a power of 2\n", i, BARSize[i]);
+ }
+ }
+ }
- DPRINTF(PCIDEV,
- "read device: %#x function: %#x register: %#x 2 bytes: data: %#x\n",
- params()->deviceNum, params()->functionNum, offset, *data);
+ plat->registerPciDevice(0, p->pci_dev, p->pci_func,
+ letoh(config.interruptLine));
}
void
-PciDev::readConfig(int offset, uint32_t *data)
+PciDev::init()
{
- if (offset >= PCI_DEVICE_SPECIFIC)
- panic("Device specific PCI config space not implemented!\n");
-
- *data = *(uint32_t*)&config.data[offset];
-
- DPRINTF(PCIDEV,
- "read device: %#x function: %#x register: %#x 4 bytes: data: %#x\n",
- params()->deviceNum, params()->functionNum, offset, *data);
+ if (!configPort)
+ panic("pci config port not connected to anything!");
+ configPort->sendStatusChange(Port::RangeChange);
+ PioDevice::init();
}
+unsigned int
+PciDev::drain(Event *de)
+{
+ unsigned int count;
+ count = pioPort->drain(de) + dmaPort->drain(de) + configPort->drain(de);
+ if (count)
+ changeState(Draining);
+ else
+ changeState(Drained);
+ return count;
+}
-void
-PciDev::writeConfig(int offset, const uint8_t data)
+Tick
+PciDev::readConfig(PacketPtr pkt)
{
+ int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
if (offset >= PCI_DEVICE_SPECIFIC)
panic("Device specific PCI config space not implemented!\n");
- DPRINTF(PCIDEV,
- "write device: %#x function: %#x reg: %#x size: 1 data: %#x\n",
- params()->deviceNum, params()->functionNum, offset, data);
-
- switch (offset) {
- case PCI0_INTERRUPT_LINE:
- config.interruptLine = data;
- case PCI_CACHE_LINE_SIZE:
- config.cacheLineSize = data;
- case PCI_LATENCY_TIMER:
- config.latencyTimer = data;
+ pkt->allocate();
+
+ switch (pkt->getSize()) {
+ case sizeof(uint8_t):
+ pkt->set<uint8_t>(config.data[offset]);
+ DPRINTF(PCIDEV,
+ "readConfig: dev %#x func %#x reg %#x 1 bytes: data = %#x\n",
+ params()->pci_dev, params()->pci_func, offset,
+ (uint32_t)pkt->get<uint8_t>());
break;
- /* Do nothing for these read-only registers */
- case PCI0_INTERRUPT_PIN:
- case PCI0_MINIMUM_GRANT:
- case PCI0_MAXIMUM_LATENCY:
- case PCI_CLASS_CODE:
- case PCI_REVISION_ID:
+ case sizeof(uint16_t):
+ pkt->set<uint16_t>(*(uint16_t*)&config.data[offset]);
+ DPRINTF(PCIDEV,
+ "readConfig: dev %#x func %#x reg %#x 2 bytes: data = %#x\n",
+ params()->pci_dev, params()->pci_func, offset,
+ (uint32_t)pkt->get<uint16_t>());
+ break;
+ case sizeof(uint32_t):
+ pkt->set<uint32_t>(*(uint32_t*)&config.data[offset]);
+ DPRINTF(PCIDEV,
+ "readConfig: dev %#x func %#x reg %#x 4 bytes: data = %#x\n",
+ params()->pci_dev, params()->pci_func, offset,
+ (uint32_t)pkt->get<uint32_t>());
break;
default:
- panic("writing to a read only register");
+ panic("invalid access size(?) for PCI configspace!\n");
}
+ pkt->makeAtomicResponse();
+ return configDelay;
+
}
void
-PciDev::writeConfig(int offset, const uint16_t data)
+PciDev::addressRanges(AddrRangeList &range_list)
{
- if (offset >= PCI_DEVICE_SPECIFIC)
- panic("Device specific PCI config space not implemented!\n");
-
- DPRINTF(PCIDEV,
- "write device: %#x function: %#x reg: %#x size: 2 data: %#x\n",
- params()->deviceNum, params()->functionNum, offset, data);
-
- switch (offset) {
- case PCI_COMMAND:
- config.command = data;
- case PCI_STATUS:
- config.status = data;
- case PCI_CACHE_LINE_SIZE:
- config.cacheLineSize = data;
- break;
- default:
- panic("writing to a read only register");
- }
+ int x = 0;
+ range_list.clear();
+ for (x = 0; x < 6; x++)
+ if (BARAddrs[x] != 0)
+ range_list.push_back(RangeSize(BARAddrs[x],BARSize[x]));
}
-
-void
-PciDev::writeConfig(int offset, const uint32_t data)
+Tick
+PciDev::writeConfig(PacketPtr pkt)
{
+ int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
if (offset >= PCI_DEVICE_SPECIFIC)
panic("Device specific PCI config space not implemented!\n");
- DPRINTF(PCIDEV,
- "write device: %#x function: %#x reg: %#x size: 4 data: %#x\n",
- params()->deviceNum, params()->functionNum, offset, data);
-
- switch (offset) {
- case PCI0_BASE_ADDR0:
- case PCI0_BASE_ADDR1:
- case PCI0_BASE_ADDR2:
- case PCI0_BASE_ADDR3:
- case PCI0_BASE_ADDR4:
- case PCI0_BASE_ADDR5:
-
- uint32_t barnum, bar_mask;
- Addr base_addr, base_size, space_base;
-
- barnum = BAR_NUMBER(offset);
-
- if (BAR_IO_SPACE(letoh(config.baseAddr[barnum]))) {
- bar_mask = BAR_IO_MASK;
- space_base = TSUNAMI_PCI0_IO;
- } else {
- bar_mask = BAR_MEM_MASK;
- space_base = TSUNAMI_PCI0_MEMORY;
- }
-
- // Writing 0xffffffff to a BAR tells the card to set the
- // value of the bar to size of memory it needs
- if (letoh(data) == 0xffffffff) {
- // This is I/O Space, bottom two bits are read only
-
- config.baseAddr[barnum] = letoh(
- (~(BARSize[barnum] - 1) & ~bar_mask) |
- (letoh(config.baseAddr[barnum]) & bar_mask));
- } else {
- config.baseAddr[barnum] = letoh(
- (letoh(data) & ~bar_mask) |
- (letoh(config.baseAddr[barnum]) & bar_mask));
-
- if (letoh(config.baseAddr[barnum]) & ~bar_mask) {
- base_addr = (letoh(data) & ~bar_mask) + space_base;
- base_size = BARSize[barnum];
- BARAddrs[barnum] = base_addr;
-
- pioPort->sendStatusChange(Port::RangeChange);
- }
+ switch (pkt->getSize()) {
+ case sizeof(uint8_t):
+ switch (offset) {
+ case PCI0_INTERRUPT_LINE:
+ config.interruptLine = pkt->get<uint8_t>();
+ break;
+ case PCI_CACHE_LINE_SIZE:
+ config.cacheLineSize = pkt->get<uint8_t>();
+ break;
+ case PCI_LATENCY_TIMER:
+ config.latencyTimer = pkt->get<uint8_t>();
+ break;
+ /* Do nothing for these read-only registers */
+ case PCI0_INTERRUPT_PIN:
+ case PCI0_MINIMUM_GRANT:
+ case PCI0_MAXIMUM_LATENCY:
+ case PCI_CLASS_CODE:
+ case PCI_REVISION_ID:
+ break;
+ default:
+ panic("writing to a read only register");
}
+ DPRINTF(PCIDEV,
+ "writeConfig: dev %#x func %#x reg %#x 1 bytes: data = %#x\n",
+ params()->pci_dev, params()->pci_func, offset,
+ (uint32_t)pkt->get<uint8_t>());
break;
-
- case PCI0_ROM_BASE_ADDR:
- if (letoh(data) == 0xfffffffe)
- config.expansionROM = htole((uint32_t)0xffffffff);
- else
- config.expansionROM = data;
+ case sizeof(uint16_t):
+ switch (offset) {
+ case PCI_COMMAND:
+ config.command = pkt->get<uint8_t>();
+ break;
+ case PCI_STATUS:
+ config.status = pkt->get<uint8_t>();
+ break;
+ case PCI_CACHE_LINE_SIZE:
+ config.cacheLineSize = pkt->get<uint8_t>();
+ break;
+ default:
+ panic("writing to a read only register");
+ }
+ DPRINTF(PCIDEV,
+ "writeConfig: dev %#x func %#x reg %#x 2 bytes: data = %#x\n",
+ params()->pci_dev, params()->pci_func, offset,
+ (uint32_t)pkt->get<uint16_t>());
break;
-
- case PCI_COMMAND:
- // This could also clear some of the error bits in the Status
- // register. However they should never get set, so lets ignore
- // it for now
- config.command = data;
+ case sizeof(uint32_t):
+ switch (offset) {
+ case PCI0_BASE_ADDR0:
+ case PCI0_BASE_ADDR1:
+ case PCI0_BASE_ADDR2:
+ case PCI0_BASE_ADDR3:
+ case PCI0_BASE_ADDR4:
+ case PCI0_BASE_ADDR5:
+ {
+ int barnum = BAR_NUMBER(offset);
+
+ if (!legacyIO[barnum]) {
+ // convert BAR values to host endianness
+ uint32_t he_old_bar = letoh(config.baseAddr[barnum]);
+ uint32_t he_new_bar = letoh(pkt->get<uint32_t>());
+
+ uint32_t bar_mask =
+ BAR_IO_SPACE(he_old_bar) ? BAR_IO_MASK : BAR_MEM_MASK;
+
+ // Writing 0xffffffff to a BAR tells the card to set the
+ // value of the bar to a bitmask indicating the size of
+ // memory it needs
+ if (he_new_bar == 0xffffffff) {
+ he_new_bar = ~(BARSize[barnum] - 1);
+ } else {
+ // does it mean something special to write 0 to a BAR?
+ he_new_bar &= ~bar_mask;
+ if (he_new_bar) {
+ BARAddrs[barnum] = BAR_IO_SPACE(he_old_bar) ?
+ platform->calcPciIOAddr(he_new_bar) :
+ platform->calcPciMemAddr(he_new_bar);
+ pioPort->sendStatusChange(Port::RangeChange);
+ }
+ }
+ config.baseAddr[barnum] = htole((he_new_bar & ~bar_mask) |
+ (he_old_bar & bar_mask));
+ }
+ }
+ break;
+
+ case PCI0_ROM_BASE_ADDR:
+ if (letoh(pkt->get<uint32_t>()) == 0xfffffffe)
+ config.expansionROM = htole((uint32_t)0xffffffff);
+ else
+ config.expansionROM = pkt->get<uint32_t>();
+ break;
+
+ case PCI_COMMAND:
+ // This could also clear some of the error bits in the Status
+ // register. However they should never get set, so lets ignore
+ // it for now
+ config.command = pkt->get<uint32_t>();
+ break;
+
+ default:
+ DPRINTF(PCIDEV, "Writing to a read only register");
+ }
+ DPRINTF(PCIDEV,
+ "writeConfig: dev %#x func %#x reg %#x 4 bytes: data = %#x\n",
+ params()->pci_dev, params()->pci_func, offset,
+ (uint32_t)pkt->get<uint32_t>());
break;
-
default:
- DPRINTF(PCIDEV, "Writing to a read only register");
+ panic("invalid access size(?) for PCI configspace!\n");
}
+ pkt->makeAtomicResponse();
+ return configDelay;
}
void
UNSERIALIZE_ARRAY(BARAddrs, sizeof(BARAddrs) / sizeof(BARAddrs[0]));
UNSERIALIZE_ARRAY(config.data,
sizeof(config.data) / sizeof(config.data[0]));
-}
+ pioPort->sendStatusChange(Port::RangeChange);
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
-
- Param<uint16_t> VendorID;
- Param<uint16_t> DeviceID;
- Param<uint16_t> Command;
- Param<uint16_t> Status;
- Param<uint8_t> Revision;
- Param<uint8_t> ProgIF;
- Param<uint8_t> SubClassCode;
- Param<uint8_t> ClassCode;
- Param<uint8_t> CacheLineSize;
- Param<uint8_t> LatencyTimer;
- Param<uint8_t> HeaderType;
- Param<uint8_t> BIST;
- Param<uint32_t> BAR0;
- Param<uint32_t> BAR1;
- Param<uint32_t> BAR2;
- Param<uint32_t> BAR3;
- Param<uint32_t> BAR4;
- Param<uint32_t> BAR5;
- Param<uint32_t> CardbusCIS;
- Param<uint16_t> SubsystemVendorID;
- Param<uint16_t> SubsystemID;
- Param<uint32_t> ExpansionROM;
- Param<uint8_t> InterruptLine;
- Param<uint8_t> InterruptPin;
- Param<uint8_t> MinimumGrant;
- Param<uint8_t> MaximumLatency;
- Param<uint32_t> BAR0Size;
- Param<uint32_t> BAR1Size;
- Param<uint32_t> BAR2Size;
- Param<uint32_t> BAR3Size;
- Param<uint32_t> BAR4Size;
- Param<uint32_t> BAR5Size;
-
-END_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigData)
-
- INIT_PARAM(VendorID, "Vendor ID"),
- INIT_PARAM(DeviceID, "Device ID"),
- INIT_PARAM_DFLT(Command, "Command Register", 0x00),
- INIT_PARAM_DFLT(Status, "Status Register", 0x00),
- INIT_PARAM_DFLT(Revision, "Device Revision", 0x00),
- INIT_PARAM_DFLT(ProgIF, "Programming Interface", 0x00),
- INIT_PARAM(SubClassCode, "Sub-Class Code"),
- INIT_PARAM(ClassCode, "Class Code"),
- INIT_PARAM_DFLT(CacheLineSize, "System Cacheline Size", 0x00),
- INIT_PARAM_DFLT(LatencyTimer, "PCI Latency Timer", 0x00),
- INIT_PARAM_DFLT(HeaderType, "PCI Header Type", 0x00),
- INIT_PARAM_DFLT(BIST, "Built In Self Test", 0x00),
- INIT_PARAM_DFLT(BAR0, "Base Address Register 0", 0x00),
- INIT_PARAM_DFLT(BAR1, "Base Address Register 1", 0x00),
- INIT_PARAM_DFLT(BAR2, "Base Address Register 2", 0x00),
- INIT_PARAM_DFLT(BAR3, "Base Address Register 3", 0x00),
- INIT_PARAM_DFLT(BAR4, "Base Address Register 4", 0x00),
- INIT_PARAM_DFLT(BAR5, "Base Address Register 5", 0x00),
- INIT_PARAM_DFLT(CardbusCIS, "Cardbus Card Information Structure", 0x00),
- INIT_PARAM_DFLT(SubsystemVendorID, "Subsystem Vendor ID", 0x00),
- INIT_PARAM_DFLT(SubsystemID, "Subsystem ID", 0x00),
- INIT_PARAM_DFLT(ExpansionROM, "Expansion ROM Base Address Register", 0x00),
- INIT_PARAM(InterruptLine, "Interrupt Line Register"),
- INIT_PARAM(InterruptPin, "Interrupt Pin Register"),
- INIT_PARAM_DFLT(MinimumGrant, "Minimum Grant", 0x00),
- INIT_PARAM_DFLT(MaximumLatency, "Maximum Latency", 0x00),
- INIT_PARAM_DFLT(BAR0Size, "Base Address Register 0 Size", 0x00),
- INIT_PARAM_DFLT(BAR1Size, "Base Address Register 1 Size", 0x00),
- INIT_PARAM_DFLT(BAR2Size, "Base Address Register 2 Size", 0x00),
- INIT_PARAM_DFLT(BAR3Size, "Base Address Register 3 Size", 0x00),
- INIT_PARAM_DFLT(BAR4Size, "Base Address Register 4 Size", 0x00),
- INIT_PARAM_DFLT(BAR5Size, "Base Address Register 5 Size", 0x00)
-
-END_INIT_SIM_OBJECT_PARAMS(PciConfigData)
-
-CREATE_SIM_OBJECT(PciConfigData)
-{
- PciConfigData *data = new PciConfigData(getInstanceName());
-
- data->config.vendor = htole(VendorID);
- data->config.device = htole(DeviceID);
- data->config.command = htole(Command);
- data->config.status = htole(Status);
- data->config.revision = htole(Revision);
- data->config.progIF = htole(ProgIF);
- data->config.subClassCode = htole(SubClassCode);
- data->config.classCode = htole(ClassCode);
- data->config.cacheLineSize = htole(CacheLineSize);
- data->config.latencyTimer = htole(LatencyTimer);
- data->config.headerType = htole(HeaderType);
- data->config.bist = htole(BIST);
-
- data->config.baseAddr0 = htole(BAR0);
- data->config.baseAddr1 = htole(BAR1);
- data->config.baseAddr2 = htole(BAR2);
- data->config.baseAddr3 = htole(BAR3);
- data->config.baseAddr4 = htole(BAR4);
- data->config.baseAddr5 = htole(BAR5);
- data->config.cardbusCIS = htole(CardbusCIS);
- data->config.subsystemVendorID = htole(SubsystemVendorID);
- data->config.subsystemID = htole(SubsystemVendorID);
- data->config.expansionROM = htole(ExpansionROM);
- data->config.interruptLine = htole(InterruptLine);
- data->config.interruptPin = htole(InterruptPin);
- data->config.minimumGrant = htole(MinimumGrant);
- data->config.maximumLatency = htole(MaximumLatency);
-
- data->BARSize[0] = BAR0Size;
- data->BARSize[1] = BAR1Size;
- data->BARSize[2] = BAR2Size;
- data->BARSize[3] = BAR3Size;
- data->BARSize[4] = BAR4Size;
- data->BARSize[5] = BAR5Size;
-
- return data;
}
-REGISTER_SIM_OBJECT("PciConfigData", PciConfigData)
-
-#endif // DOXYGEN_SHOULD_SKIP_THIS
projects / gem5.git / blobdiff