#include <limits>
#include <string>
+#ifdef SINIC_VTOPHYS
#include "arch/vtophys.hh"
+#endif
+#include "base/compiler.hh"
+#include "base/debug.hh"
#include "base/inet.hh"
-#include "cpu/thread_context.hh"
-#include "cpu/intr_control.hh"
+#include "base/types.hh"
+#include "config/the_isa.hh"
+#include "debug/EthernetAll.hh"
#include "dev/etherlink.hh"
#include "dev/sinic.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
-#include "sim/debug.hh"
#include "sim/eventq.hh"
-#include "sim/host.hh"
#include "sim/stats.hh"
using namespace std;
// Sinic PCI Device
//
Base::Base(const Params *p)
- : PciDev(p), rxEnable(false), txEnable(false), clock(p->clock),
+ : EtherDevBase(p), rxEnable(false), txEnable(false),
intrDelay(p->intr_delay), intrTick(0), cpuIntrEnable(false),
cpuPendingIntr(false), intrEvent(0), interface(NULL)
{
void
Device::regStats()
{
- rxBytes
- .name(name() + ".rxBytes")
- .desc("Bytes Received")
- .prereq(rxBytes)
- ;
-
- rxBandwidth
- .name(name() + ".rxBandwidth")
- .desc("Receive Bandwidth (bits/s)")
- .precision(0)
- .prereq(rxBytes)
- ;
-
- rxPackets
- .name(name() + ".rxPackets")
- .desc("Number of Packets Received")
- .prereq(rxBytes)
- ;
-
- rxPacketRate
- .name(name() + ".rxPPS")
- .desc("Packet Reception Rate (packets/s)")
- .precision(0)
- .prereq(rxBytes)
- ;
-
- rxIpPackets
- .name(name() + ".rxIpPackets")
- .desc("Number of IP Packets Received")
- .prereq(rxBytes)
- ;
-
- rxTcpPackets
- .name(name() + ".rxTcpPackets")
- .desc("Number of Packets Received")
- .prereq(rxBytes)
- ;
-
- rxUdpPackets
- .name(name() + ".rxUdpPackets")
- .desc("Number of UDP Packets Received")
- .prereq(rxBytes)
- ;
-
- rxIpChecksums
- .name(name() + ".rxIpChecksums")
- .desc("Number of rx IP Checksums done by device")
- .precision(0)
- .prereq(rxBytes)
- ;
-
- rxTcpChecksums
- .name(name() + ".rxTcpChecksums")
- .desc("Number of rx TCP Checksums done by device")
- .precision(0)
- .prereq(rxBytes)
- ;
-
- rxUdpChecksums
- .name(name() + ".rxUdpChecksums")
- .desc("Number of rx UDP Checksums done by device")
- .precision(0)
- .prereq(rxBytes)
- ;
-
- totBandwidth
- .name(name() + ".totBandwidth")
- .desc("Total Bandwidth (bits/s)")
- .precision(0)
- .prereq(totBytes)
- ;
-
- totPackets
- .name(name() + ".totPackets")
- .desc("Total Packets")
- .precision(0)
- .prereq(totBytes)
- ;
-
- totBytes
- .name(name() + ".totBytes")
- .desc("Total Bytes")
- .precision(0)
- .prereq(totBytes)
- ;
-
- totPacketRate
- .name(name() + ".totPPS")
- .desc("Total Tranmission Rate (packets/s)")
- .precision(0)
- .prereq(totBytes)
- ;
-
- txBytes
- .name(name() + ".txBytes")
- .desc("Bytes Transmitted")
- .prereq(txBytes)
- ;
-
- txBandwidth
- .name(name() + ".txBandwidth")
- .desc("Transmit Bandwidth (bits/s)")
- .precision(0)
- .prereq(txBytes)
- ;
-
- txPackets
- .name(name() + ".txPackets")
- .desc("Number of Packets Transmitted")
- .prereq(txBytes)
- ;
-
- txPacketRate
- .name(name() + ".txPPS")
- .desc("Packet Tranmission Rate (packets/s)")
- .precision(0)
- .prereq(txBytes)
- ;
-
- txIpPackets
- .name(name() + ".txIpPackets")
- .desc("Number of IP Packets Transmitted")
- .prereq(txBytes)
- ;
-
- txTcpPackets
- .name(name() + ".txTcpPackets")
- .desc("Number of TCP Packets Transmitted")
- .prereq(txBytes)
- ;
-
- txUdpPackets
- .name(name() + ".txUdpPackets")
- .desc("Number of Packets Transmitted")
- .prereq(txBytes)
- ;
-
- txIpChecksums
- .name(name() + ".txIpChecksums")
- .desc("Number of tx IP Checksums done by device")
- .precision(0)
- .prereq(txBytes)
- ;
-
- txTcpChecksums
- .name(name() + ".txTcpChecksums")
- .desc("Number of tx TCP Checksums done by device")
- .precision(0)
- .prereq(txBytes)
- ;
-
- txUdpChecksums
- .name(name() + ".txUdpChecksums")
- .desc("Number of tx UDP Checksums done by device")
- .precision(0)
- .prereq(txBytes)
- ;
-
- txBandwidth = txBytes * Stats::constant(8) / simSeconds;
- rxBandwidth = rxBytes * Stats::constant(8) / simSeconds;
- totBandwidth = txBandwidth + rxBandwidth;
- totBytes = txBytes + rxBytes;
- totPackets = txPackets + rxPackets;
- txPacketRate = txPackets / simSeconds;
- rxPacketRate = rxPackets / simSeconds;
+ Base::regStats();
_maxVnicDistance = 0;
void
Device::resetStats()
{
+ Base::resetStats();
+
_maxVnicDistance = 0;
}
prepareRead(cpu, index);
- uint64_t value = 0;
+ uint64_t value M5_VAR_USED = 0;
if (pkt->getSize() == 4) {
uint32_t reg = regData32(raddr);
pkt->set(reg);
interrupts &= ~Regs::Intr_TxLow;
if (interrupts) {
- Tick when = curTick;
+ Tick when = curTick();
if ((interrupts & Regs::Intr_NoDelay) == 0)
when += intrDelay;
cpuIntrPost(when);
regs.IntrStatus, regs.IntrMask, regs.IntrStatus & regs.IntrMask);
if (regs.IntrStatus & regs.IntrMask)
- cpuIntrPost(curTick);
+ cpuIntrPost(curTick());
else
cpuIntrClear();
}
* @todo this warning should be removed and the intrTick code should
* be fixed.
*/
- assert(when >= curTick);
- assert(intrTick >= curTick || intrTick == 0);
+ assert(when >= curTick());
+ assert(intrTick >= curTick() || intrTick == 0);
if (!cpuIntrEnable) {
DPRINTF(EthernetIntr, "interrupts not enabled.\n",
intrTick);
}
intrTick = when;
- if (intrTick < curTick) {
- debug_break();
- intrTick = curTick;
+ if (intrTick < curTick()) {
+ Debug::breakpoint();
+ intrTick = curTick();
}
DPRINTF(EthernetIntr, "going to schedule an interrupt for intrTick=%d\n",
void
Base::cpuInterrupt()
{
- assert(intrTick == curTick);
+ assert(intrTick == curTick());
// Whether or not there's a pending interrupt, we don't care about
// it anymore
cpuIntrEnable = regs.Config & Regs::Config_IntEn;
if (cpuIntrEnable) {
if (regs.IntrStatus & regs.IntrMask)
- cpuIntrPost(curTick);
+ cpuIntrPost(curTick());
} else {
cpuIntrClear();
}
DPRINTF(EthernetSM, "rxKick: rxState=%s (rxFifo.size=%d)\n",
RxStateStrings[rxState], rxFifo.size());
- if (rxKickTick > curTick) {
+ if (rxKickTick > curTick()) {
DPRINTF(EthernetSM, "rxKick: exiting, can't run till %d\n",
rxKickTick);
return;
VirtualReg *vn = &virtualRegs[i];
bool busy = Regs::get_RxDone_Busy(vn->RxDone);
if (vn->rxIndex != end) {
+#ifndef NDEBUG
bool dirty = vn->rxPacketOffset > 0;
const char *status;
i, status, vn->rxUnique,
rxFifo.countPacketsBefore(vn->rxIndex),
vn->rxIndex->slack);
+#endif
} else if (busy) {
DPRINTF(EthernetSM, "vnic %d unmapped (rxunique %d)\n",
i, vn->rxUnique);
break;
case rxBeginCopy:
- if (dmaPending() || getState() != Running)
+ if (dmaPending() || getDrainState() != Drainable::Running)
goto exit;
rxDmaAddr = params()->platform->pciToDma(
Regs::get_RxData_Addr(vnic->RxData));
- rxDmaLen = min<int>(Regs::get_RxData_Len(vnic->RxData),
- vnic->rxPacketBytes);
+ rxDmaLen = min<unsigned>(Regs::get_RxData_Len(vnic->RxData),
+ vnic->rxPacketBytes);
/*
* if we're doing zero/delay copy and we're below the fifo
DPRINTF(EthernetSM, "txKick: txState=%s (txFifo.size=%d)\n",
TxStateStrings[txState], txFifo.size());
- if (txKickTick > curTick) {
+ if (txKickTick > curTick()) {
DPRINTF(EthernetSM, "txKick: exiting, can't run till %d\n",
txKickTick);
return;
break;
case txBeginCopy:
- if (dmaPending() || getState() != Running)
+ if (dmaPending() || getDrainState() != Drainable::Running)
goto exit;
txDmaAddr = params()->platform->pciToDma(
DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n");
- reschedule(txEvent, curTick + ticks(1), true);
+ reschedule(txEvent, clockEdge(Cycles(1)), true);
}
bool
}
void
-Device::resume()
+Device::drainResume()
{
- SimObject::resume();
+ Drainable::drainResume();
// During drain we could have left the state machines in a waiting state and
// they wouldn't get out until some other event occured to kick them.
void
Base::serialize(std::ostream &os)
{
- // Serialize the PciDev base class
- PciDev::serialize(os);
+ // Serialize the PciDevice base class
+ PciDevice::serialize(os);
SERIALIZE_SCALAR(rxEnable);
SERIALIZE_SCALAR(txEnable);
void
Base::unserialize(Checkpoint *cp, const std::string §ion)
{
- // Unserialize the PciDev base class
- PciDev::unserialize(cp, section);
+ // Unserialize the PciDevice base class
+ PciDevice::unserialize(cp, section);
UNSERIALIZE_SCALAR(rxEnable);
UNSERIALIZE_SCALAR(txEnable);
{
int count;
- // Serialize the PciDev base class
+ // Serialize the PciDevice base class
Base::serialize(os);
if (rxState == rxCopy)
* If there's a pending transmit, store the time so we can
* reschedule it later
*/
- Tick transmitTick = txEvent.scheduled() ? txEvent.when() - curTick : 0;
+ Tick transmitTick = txEvent.scheduled() ? txEvent.when() - curTick() : 0;
SERIALIZE_SCALAR(transmitTick);
}
void
Device::unserialize(Checkpoint *cp, const std::string §ion)
{
- // Unserialize the PciDev base class
+ // Unserialize the PciDevice base class
Base::unserialize(cp, section);
/*
Tick transmitTick;
UNSERIALIZE_SCALAR(transmitTick);
if (transmitTick)
- schedule(txEvent, curTick + transmitTick);
+ schedule(txEvent, curTick() + transmitTick);
- pioPort->sendStatusChange(Port::RangeChange);
+ pioPort.sendRangeChange();
}
-/* namespace Sinic */ }
+} // namespace Sinic
Sinic::Device *
SinicParams::create()
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