* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
*/
#include <deque>
#include <limits>
#include <string>
+#include "arch/vtophys.hh"
#include "base/inet.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "cpu/intr_control.hh"
#include "dev/etherlink.hh"
#include "dev/sinic.hh"
-#include "dev/pciconfigall.hh"
#include "mem/packet.hh"
-#include "sim/builder.hh"
+#include "mem/packet_access.hh"
#include "sim/debug.hh"
#include "sim/eventq.hh"
#include "sim/host.hh"
#include "sim/stats.hh"
-#include "arch/vtophys.hh"
using namespace Net;
using namespace TheISA;
//
// Sinic PCI Device
//
-Base::Base(Params *p)
+Base::Base(const Params *p)
: PciDev(p), rxEnable(false), txEnable(false), clock(p->clock),
intrDelay(p->intr_delay), intrTick(0), cpuIntrEnable(false),
cpuPendingIntr(false), intrEvent(0), interface(NULL)
{
}
-Device::Device(Params *p)
+Device::Device(const Params *p)
: Base(p), rxUnique(0), txUnique(0),
virtualRegs(p->virtual_count < 1 ? 1 : p->virtual_count),
rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size),
dmaReadDelay(p->dma_read_delay), dmaReadFactor(p->dma_read_factor),
dmaWriteDelay(p->dma_write_delay), dmaWriteFactor(p->dma_write_factor)
{
+ interface = new Interface(name() + ".int0", this);
reset();
}
rxPacketRate = rxPackets / simSeconds;
}
+EtherInt*
+Device::getEthPort(const std::string &if_name, int idx)
+{
+ if (if_name == "interface") {
+ if (interface->getPeer())
+ panic("interface already connected to\n");
+
+ return interface;
+ }
+ return NULL;
+}
+
+
void
Device::prepareIO(int cpu, int index)
{
* I/O read of device register
*/
Tick
-Device::read(Packet *pkt)
+Device::read(PacketPtr pkt)
{
assert(config.command & PCI_CMD_MSE);
- assert(pkt->addr >= BARAddrs[0] && pkt->size < BARSize[0]);
+ assert(pkt->getAddr() >= BARAddrs[0] && pkt->getSize() < BARSize[0]);
int cpu = pkt->req->getCpuNum();
- Addr daddr = pkt->addr - BARAddrs[0];
+ Addr daddr = pkt->getAddr() - BARAddrs[0];
Addr index = daddr >> Regs::VirtualShift;
Addr raddr = daddr & Regs::VirtualMask;
- pkt->time += pioDelay;
pkt->allocate();
if (!regValid(raddr))
panic("invalid register: cpu=%d vnic=%d da=%#x pa=%#x size=%d",
- cpu, index, daddr, pkt->addr, pkt->size);
+ cpu, index, daddr, pkt->getAddr(), pkt->getSize());
const Regs::Info &info = regInfo(raddr);
if (!info.read)
panic("read %s (write only): "
"cpu=%d vnic=%d da=%#x pa=%#x size=%d",
- info.name, cpu, index, daddr, pkt->addr, pkt->size);
+ info.name, cpu, index, daddr, pkt->getAddr(), pkt->getSize());
panic("read %s (invalid size): "
"cpu=%d vnic=%d da=%#x pa=%#x size=%d",
- info.name, cpu, index, daddr, pkt->addr, pkt->size);
+ info.name, cpu, index, daddr, pkt->getAddr(), pkt->getSize());
prepareRead(cpu, index);
uint64_t value = 0;
- if (pkt->size == 4) {
+ if (pkt->getSize() == 4) {
uint32_t reg = regData32(raddr);
pkt->set(reg);
value = reg;
}
- if (pkt->size == 8) {
+ if (pkt->getSize() == 8) {
uint64_t reg = regData64(raddr);
pkt->set(reg);
value = reg;
DPRINTF(EthernetPIO,
"read %s: cpu=%d vnic=%d da=%#x pa=%#x size=%d val=%#x\n",
- info.name, cpu, index, daddr, pkt->addr, pkt->size, value);
+ info.name, cpu, index, daddr, pkt->getAddr(), pkt->getSize(), value);
// reading the interrupt status register has the side effect of
// clearing it
* I/O write of device register
*/
Tick
-Device::write(Packet *pkt)
+Device::write(PacketPtr pkt)
{
assert(config.command & PCI_CMD_MSE);
- assert(pkt->addr >= BARAddrs[0] && pkt->size < BARSize[0]);
+ assert(pkt->getAddr() >= BARAddrs[0] && pkt->getSize() < BARSize[0]);
int cpu = pkt->req->getCpuNum();
- Addr daddr = pkt->addr - BARAddrs[0];
+ Addr daddr = pkt->getAddr() - BARAddrs[0];
Addr index = daddr >> Regs::VirtualShift;
Addr raddr = daddr & Regs::VirtualMask;
- pkt->time += pioDelay;
-
if (!regValid(raddr))
panic("invalid register: cpu=%d, da=%#x pa=%#x size=%d",
- cpu, daddr, pkt->addr, pkt->size);
+ cpu, daddr, pkt->getAddr(), pkt->getSize());
const Regs::Info &info = regInfo(raddr);
if (!info.write)
panic("write %s (read only): "
"cpu=%d vnic=%d da=%#x pa=%#x size=%d",
- info.name, cpu, index, daddr, pkt->addr, pkt->size);
+ info.name, cpu, index, daddr, pkt->getAddr(), pkt->getSize());
- if (pkt->size != info.size)
+ if (pkt->getSize() != info.size)
panic("write %s (invalid size): "
"cpu=%d vnic=%d da=%#x pa=%#x size=%d",
- info.name, cpu, index, daddr, pkt->addr, pkt->size);
+ info.name, cpu, index, daddr, pkt->getAddr(), pkt->getSize());
VirtualReg &vnic = virtualRegs[index];
DPRINTF(EthernetPIO,
"write %s vnic %d: cpu=%d val=%#x da=%#x pa=%#x size=%d\n",
info.name, index, cpu, info.size == 4 ? pkt->get<uint32_t>() :
- pkt->get<uint64_t>(), daddr, pkt->addr, pkt->size);
+ pkt->get<uint64_t>(), daddr, pkt->getAddr(), pkt->getSize());
prepareWrite(cpu, index);
if (intrEvent)
intrEvent->squash();
- intrEvent = new IntrEvent(this, true);
- intrEvent->schedule(intrTick);
+ intrEvent = new IntrEvent(this, intrTick, true);
}
void
regs.TxFifoSize = params()->tx_fifo_size;
regs.RxFifoMark = params()->rx_fifo_threshold;
regs.TxFifoMark = params()->tx_fifo_threshold;
- regs.HwAddr = params()->eaddr;
+ regs.HwAddr = params()->hardware_address;
rxList.clear();
rxBusy.clear();
break;
case rxBeginCopy:
- if (dmaPending())
+ if (dmaPending() || getState() != Running)
goto exit;
rxDmaAddr = params()->platform->pciToDma(
break;
case txBeginCopy:
- if (dmaPending())
+ if (dmaPending() || getState() != Running)
goto exit;
txDmaAddr = params()->platform->pciToDma(
DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n");
- if (txEvent.scheduled())
- txEvent.reschedule(curTick + cycles(1));
- else
- txEvent.schedule(curTick + cycles(1));
+ txEvent.reschedule(curTick + ticks(1), true);
}
bool
return true;
}
+void
+Device::resume()
+{
+ SimObject::resume();
+
+ // During drain we could have left the state machines in a waiting state and
+ // they wouldn't get out until some other event occured to kick them.
+ // This way they'll get out immediately
+ txKick();
+ rxKick();
+}
+
//=====================================================================
//
//
Tick intrEventTick;
UNSERIALIZE_SCALAR(intrEventTick);
if (intrEventTick) {
- intrEvent = new IntrEvent(this, true);
- intrEvent->schedule(intrEventTick);
+ intrEvent = new IntrEvent(this, intrEventTick, true);
}
}
}
+/* namespace Sinic */ }
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(Interface)
-
- SimObjectParam<EtherInt *> peer;
- SimObjectParam<Device *> device;
-
-END_DECLARE_SIM_OBJECT_PARAMS(Interface)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(Interface)
-
- INIT_PARAM_DFLT(peer, "peer interface", NULL),
- INIT_PARAM(device, "Ethernet device of this interface")
-
-END_INIT_SIM_OBJECT_PARAMS(Interface)
-
-CREATE_SIM_OBJECT(Interface)
-{
- Interface *dev_int = new Interface(getInstanceName(), device);
-
- EtherInt *p = (EtherInt *)peer;
- if (p) {
- dev_int->setPeer(p);
- p->setPeer(dev_int);
- }
-
- return dev_int;
-}
-
-REGISTER_SIM_OBJECT("SinicInt", Interface)
-
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(Device)
-
-
- SimObjectParam<System *> system;
- SimObjectParam<Platform *> platform;
- SimObjectParam<PciConfigAll *> configspace;
- SimObjectParam<PciConfigData *> configdata;
- Param<uint32_t> pci_bus;
- Param<uint32_t> pci_dev;
- Param<uint32_t> pci_func;
- Param<Tick> pio_latency;
- Param<Tick> intr_delay;
-
- Param<Tick> clock;
- Param<Tick> dma_read_delay;
- Param<Tick> dma_read_factor;
- Param<Tick> dma_write_delay;
- Param<Tick> dma_write_factor;
-
- Param<Tick> rx_delay;
- Param<Tick> tx_delay;
- Param<uint32_t> rx_max_copy;
- Param<uint32_t> tx_max_copy;
- Param<uint32_t> rx_max_intr;
- Param<uint32_t> rx_fifo_size;
- Param<uint32_t> tx_fifo_size;
- Param<uint32_t> rx_fifo_threshold;
- Param<uint32_t> rx_fifo_low_mark;
- Param<uint32_t> tx_fifo_high_mark;
- Param<uint32_t> tx_fifo_threshold;
-
- Param<bool> rx_filter;
- Param<std::string> hardware_address;
- Param<bool> rx_thread;
- Param<bool> tx_thread;
- Param<bool> rss;
- Param<uint32_t> virtual_count;
- Param<bool> zero_copy;
- Param<bool> delay_copy;
- Param<bool> virtual_addr;
-
-END_DECLARE_SIM_OBJECT_PARAMS(Device)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(Device)
-
-
- INIT_PARAM(system, "System pointer"),
- INIT_PARAM(platform, "Platform pointer"),
- INIT_PARAM(configspace, "PCI Configspace"),
- INIT_PARAM(configdata, "PCI Config data"),
- INIT_PARAM(pci_bus, "PCI bus ID"),
- INIT_PARAM(pci_dev, "PCI device number"),
- INIT_PARAM(pci_func, "PCI function code"),
- INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
- INIT_PARAM(intr_delay, "Interrupt Delay"),
- INIT_PARAM(clock, "State machine cycle time"),
-
- INIT_PARAM(dma_read_delay, "fixed delay for dma reads"),
- INIT_PARAM(dma_read_factor, "multiplier for dma reads"),
- INIT_PARAM(dma_write_delay, "fixed delay for dma writes"),
- INIT_PARAM(dma_write_factor, "multiplier for dma writes"),
-
- INIT_PARAM(rx_delay, "Receive Delay"),
- INIT_PARAM(tx_delay, "Transmit Delay"),
- INIT_PARAM(rx_max_copy, "rx max copy"),
- INIT_PARAM(tx_max_copy, "rx max copy"),
- INIT_PARAM(rx_max_intr, "rx max intr"),
- INIT_PARAM(rx_fifo_size, "max size in bytes of rxFifo"),
- INIT_PARAM(tx_fifo_size, "max size in bytes of txFifo"),
- INIT_PARAM(rx_fifo_threshold, "max size in bytes of rxFifo"),
- INIT_PARAM(rx_fifo_low_mark, "max size in bytes of rxFifo"),
- INIT_PARAM(tx_fifo_high_mark, "max size in bytes of txFifo"),
- INIT_PARAM(tx_fifo_threshold, "max size in bytes of txFifo"),
-
- INIT_PARAM(rx_filter, "Enable Receive Filter"),
- INIT_PARAM(hardware_address, "Ethernet Hardware Address"),
- INIT_PARAM(rx_thread, ""),
- INIT_PARAM(tx_thread, ""),
- INIT_PARAM(rss, ""),
- INIT_PARAM(virtual_count, ""),
- INIT_PARAM(zero_copy, ""),
- INIT_PARAM(delay_copy, ""),
- INIT_PARAM(virtual_addr, "")
-
-END_INIT_SIM_OBJECT_PARAMS(Device)
-
-
-CREATE_SIM_OBJECT(Device)
+Sinic::Device *
+SinicParams::create()
{
- Device::Params *params = new Device::Params;
- params->name = getInstanceName();
- params->platform = platform;
- params->system = system;
- params->configSpace = configspace;
- params->configData = configdata;
- params->busNum = pci_bus;
- params->deviceNum = pci_dev;
- params->functionNum = pci_func;
- params->pio_delay = pio_latency;
- params->intr_delay = intr_delay;
- params->clock = clock;
-
- params->dma_read_delay = dma_read_delay;
- params->dma_read_factor = dma_read_factor;
- params->dma_write_delay = dma_write_delay;
- params->dma_write_factor = dma_write_factor;
-
- params->tx_delay = tx_delay;
- params->rx_delay = rx_delay;
- params->rx_max_copy = rx_max_copy;
- params->tx_max_copy = tx_max_copy;
- params->rx_max_intr = rx_max_intr;
- params->rx_fifo_size = rx_fifo_size;
- params->tx_fifo_size = tx_fifo_size;
- params->rx_fifo_threshold = rx_fifo_threshold;
- params->rx_fifo_low_mark = rx_fifo_low_mark;
- params->tx_fifo_high_mark = tx_fifo_high_mark;
- params->tx_fifo_threshold = tx_fifo_threshold;
-
- params->rx_filter = rx_filter;
- params->eaddr = hardware_address;
- params->rx_thread = rx_thread;
- params->tx_thread = tx_thread;
- params->rss = rss;
- params->virtual_count = virtual_count;
- params->zero_copy = zero_copy;
- params->delay_copy = delay_copy;
- params->virtual_addr = virtual_addr;
-
- return new Device(params);
+ return new Sinic::Device(this);
}
-
-REGISTER_SIM_OBJECT("Sinic", Device)
-
-/* namespace Sinic */ }
projects / gem5.git / blobdiff