//
// Sinic PCI Device
//
-Base::Base(Params *p)
+Base::Base(const Params *p)
: PciDev(p), rxEnable(false), txEnable(false), clock(p->clock),
intrDelay(p->intr_delay), intrTick(0), cpuIntrEnable(false),
cpuPendingIntr(false), intrEvent(0), interface(NULL)
{
}
-Device::Device(Params *p)
+Device::Device(const Params *p)
: Base(p), rxUnique(0), txUnique(0),
virtualRegs(p->virtual_count < 1 ? 1 : p->virtual_count),
rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size),
dmaReadDelay(p->dma_read_delay), dmaReadFactor(p->dma_read_factor),
dmaWriteDelay(p->dma_write_delay), dmaWriteFactor(p->dma_write_factor)
{
+ interface = new Interface(name() + ".int0", this);
reset();
}
rxPacketRate = rxPackets / simSeconds;
}
+EtherInt*
+Device::getEthPort(const std::string &if_name, int idx)
+{
+ if (if_name == "interface") {
+ if (interface->getPeer())
+ panic("interface already connected to\n");
+
+ return interface;
+ }
+ return NULL;
+}
+
+
void
Device::prepareIO(int cpu, int index)
{
DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n");
- txEvent.reschedule(curTick + cycles(1), true);
+ txEvent.reschedule(curTick + ticks(1), true);
}
bool
/* namespace Sinic */ }
-Sinic::Interface *
-SinicIntParams::create()
-{
- using namespace Sinic;
-
- Interface *dev_int = new Interface(name, device);
-
- if (peer) {
- dev_int->setPeer(peer);
- peer->setPeer(dev_int);
- }
-
- return dev_int;
-}
-
Sinic::Device *
SinicParams::create()
{