Config: Enable using O3 CPU and Ruby in SE mode

[gem5.git] / src / dev / uart.cc

diff --git a/src/dev/uart.cc b/src/dev/uart.cc
index 4a9f2b505000bbcdb3599a1291029b1a1b7f4ba5..ab0ebde2cdb8926663d021d17d765e68847bedc8 100644 (file)
--- a/src/dev/uart.cc
+++ b/src/dev/uart.cc
@@ -24,29 +24,25 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
  */
 
 /** @file
  * Implements a base class for UARTs
  */
 
-#include "dev/simconsole.hh"
-#include "dev/uart.hh"
 #include "dev/platform.hh"
-#include "sim/builder.hh"
+#include "dev/terminal.hh"
+#include "dev/uart.hh"
 
 using namespace std;
 
-Uart::Uart(Params *p)
-    : BasicPioDevice(p), platform(p->platform), cons(p->cons)
+Uart::Uart(const Params *p)
+    : BasicPioDevice(p), platform(p->platform), term(p->terminal)
 {
-
     status = 0;
 
     // set back pointers
-    cons->uart = this;
-    platform->uart = this;
+    term->uart = this;
 }
-
-DEFINE_SIM_OBJECT_CLASS_NAME("Uart", Uart)
-