arm: Wire up the GIC with the platform in the base class

[gem5.git] / src / dev / uart8250.cc

diff --git a/src/dev/uart8250.cc b/src/dev/uart8250.cc
index f131ab69f966b6bad90782480d5e68b0f58c2ca4..e840d2a56a52cbb0e633abb49b5fcf870ec9cd69 100644 (file)
--- a/src/dev/uart8250.cc
+++ b/src/dev/uart8250.cc
@@ -36,9 +36,9 @@
 #include <vector>
 
 #include "base/inifile.hh"
-#include "base/str.hh"        // for to_number
 #include "base/trace.hh"
 #include "config/the_isa.hh"
+#include "debug/Uart.hh"
 #include "dev/platform.hh"
 #include "dev/terminal.hh"
 #include "dev/uart8250.hh"
@@ -68,7 +68,7 @@ Uart8250::IntrEvent::process()
        DPRINTF(Uart, "UART InterEvent, interrupting\n");
        uart->platform->postConsoleInt();
        uart->status |= intrBit;
-       uart->lastTxInt = curTick;
+       uart->lastTxInt = curTick();
     }
     else
        DPRINTF(Uart, "UART InterEvent, not interrupting\n");
@@ -90,21 +90,20 @@ Uart8250::IntrEvent::process()
 void
 Uart8250::IntrEvent::scheduleIntr()
 {
-    static const Tick interval = 225 * Clock::Int::ns;
+    static const Tick interval = 225 * SimClock::Int::ns;
     DPRINTF(Uart, "Scheduling IER interrupt for %#x, at cycle %lld\n", intrBit,
-            curTick + interval);
+            curTick() + interval);
     if (!scheduled())
-        uart->schedule(this, curTick + interval);
+        uart->schedule(this, curTick() + interval);
     else
-        uart->reschedule(this, curTick + interval);
+        uart->reschedule(this, curTick() + interval);
 }
 
 
 Uart8250::Uart8250(const Params *p)
-    : Uart(p), IER(0), DLAB(0), LCR(0), MCR(0), lastTxInt(0),
+    : Uart(p, 8), IER(0), DLAB(0), LCR(0), MCR(0), lastTxInt(0),
       txIntrEvent(this, TX_INT), rxIntrEvent(this, RX_INT)
 {
-    pioSize = 8;
 }
 
 Tick
@@ -114,7 +113,6 @@ Uart8250::read(PacketPtr pkt)
     assert(pkt->getSize() == 1);
 
     Addr daddr = pkt->getAddr() - pioAddr;
-    pkt->allocate();
 
     DPRINTF(Uart, " read register %#x\n", daddr);
 
@@ -161,6 +159,7 @@ Uart8250::read(PacketPtr pkt)
             pkt->set(LCR);
             break;
         case 0x4: // Modem Control Register (MCR)
+            pkt->set(MCR);
             break;
         case 0x5: // Line Status Register (LSR)
             uint8_t lsr;
@@ -217,13 +216,13 @@ Uart8250::write(PacketPtr pkt)
                 if (UART_IER_THRI & IER)
                 {
                     DPRINTF(Uart, "IER: IER_THRI set, scheduling TX intrrupt\n");
-                    if (curTick - lastTxInt > 225 * Clock::Int::ns) {
+                    if (curTick() - lastTxInt > 225 * SimClock::Int::ns) {
                         DPRINTF(Uart, "-- Interrupting Immediately... %d,%d\n",
-                                curTick, lastTxInt);
+                                curTick(), lastTxInt);
                         txIntrEvent.process();
                     } else {
                         DPRINTF(Uart, "-- Delaying interrupt... %d,%d\n",
-                                curTick, lastTxInt);
+                                curTick(), lastTxInt);
                         txIntrEvent.scheduleIntr();
                     }
                 }
@@ -284,16 +283,14 @@ Uart8250::dataAvailable()
 
 }
 
-void
-Uart8250::addressRanges(AddrRangeList &range_list)
+AddrRangeList
+Uart8250::getAddrRanges() const
 {
-    assert(pioSize != 0);
-    range_list.clear();
-    range_list.push_back(RangeSize(pioAddr, pioSize));
+    AddrRangeList ranges;
+    ranges.push_back(RangeSize(pioAddr, pioSize));
+    return ranges;
 }
 
-
-
 void
 Uart8250::serialize(ostream &os)
 {