sim: Include object header files in SWIG interfaces

[gem5.git] / src / dev / x86 / I82094AA.py

diff --git a/src/dev/x86/I82094AA.py b/src/dev/x86/I82094AA.py
index 3b076a9d68ff50f4be1fa18738079c9313e8fac2..7e71cdfc1af237a16513eae1cfdd10b8bf983684 100644 (file)
--- a/src/dev/x86/I82094AA.py
+++ b/src/dev/x86/I82094AA.py
@@ -34,6 +34,7 @@ from X86IntPin import X86IntSinkPin
 class I82094AA(BasicPioDevice):
     type = 'I82094AA'
     cxx_class = 'X86ISA::I82094AA'
+    cxx_header = "dev/x86/i82094aa.hh"
     apic_id = Param.Int(1, 'APIC id for this IO APIC')
     int_master = MasterPort("Port for sending interrupt messages")
     int_latency = Param.Latency('1ns', \