X86: Configure the first PCI interrupt.

[gem5.git] / src / dev / x86 / SouthBridge.py

diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py
index be927614536749fc69a657022e75e36750b8876c..d89ed9dc6134b59f473dd010916a9f4cb9b1d911 100644 (file)
--- a/src/dev/x86/SouthBridge.py
+++ b/src/dev/x86/SouthBridge.py
@@ -87,6 +87,8 @@ class SouthBridge(SimObject):
     ide.BAR3LegacyIO = True
     ide.BAR4 = 1
     ide.Command = 1
+    ide.InterruptLine = 14
+    ide.InterruptPin = 1
 
     def attachIO(self, bus):
         # Route interupt signals