MEM: Introduce the master/slave port roles in the Python classes

[gem5.git] / src / dev / x86 / intdev.hh

diff --git a/src/dev/x86/intdev.hh b/src/dev/x86/intdev.hh
index ba9a073a41da025bf1f9c1a1f4e41dfbdfead496..05b4d12a1a8039be9d69430fb7dd3cf8aa2eb384 100644 (file)
--- a/src/dev/x86/intdev.hh
+++ b/src/dev/x86/intdev.hh
@@ -31,17 +31,23 @@
 #ifndef __DEV_X86_INTDEV_HH__
 #define __DEV_X86_INTDEV_HH__
 
-#include <assert.h>
+#include <cassert>
+#include <list>
 #include <string>
 
+#include "arch/x86/intmessage.hh"
 #include "arch/x86/x86_traits.hh"
 #include "mem/mem_object.hh"
 #include "mem/mport.hh"
+#include "params/X86IntLine.hh"
+#include "params/X86IntSinkPin.hh"
+#include "params/X86IntSourcePin.hh"
 #include "sim/sim_object.hh"
-#include "params/X86IntPin.hh"
 
 namespace X86ISA {
 
+typedef std::list<int> ApicList;
+
 class IntDev
 {
   protected:
@@ -57,10 +63,9 @@ class IntDev
         {
         }
 
-        void getDeviceAddressRanges(AddrRangeList &resp, bool &snoop)
+        AddrRangeList getAddrRanges()
         {
-            snoop = false;
-            device->getIntAddrRange(resp);
+            return device->getIntAddrRange();
         }
 
         Tick recvMessage(PacketPtr pkt)
@@ -68,13 +73,15 @@ class IntDev
             return device->recvMessage(pkt);
         }
 
-        void recvStatusChange(Status status)
+        Tick recvResponse(PacketPtr pkt)
         {
-            if (status == RangeChange) {
-                sendStatusChange(Port::RangeChange);
-            }
+            return device->recvResponse(pkt);
         }
 
+        // This is x86 focused, so if this class becomes generic, this would
+        // need to be moved into a subclass.
+        void sendMessage(ApicList apics,
+                TriggerIntMessage message, bool timing);
     };
 
     IntPort * intPort;
@@ -83,7 +90,7 @@ class IntDev
     IntDev(MemObject * parent, Tick latency = 0)
     {
         if (parent != NULL) {
-            intPort = new IntPort(parent->name() + ".int_port",
+            intPort = new IntPort(parent->name() + ".int_master",
                     parent, this, latency);
         } else {
             intPort = NULL;
@@ -93,12 +100,26 @@ class IntDev
     virtual ~IntDev()
     {}
 
+    virtual void init();
+
     virtual void
     signalInterrupt(int line)
     {
         panic("signalInterrupt not implemented.\n");
     }
 
+    virtual void
+    raiseInterruptPin(int number)
+    {
+        panic("raiseInterruptPin not implemented.\n");
+    }
+
+    virtual void
+    lowerInterruptPin(int number)
+    {
+        panic("lowerInterruptPin not implemented.\n");
+    }
+
     virtual Tick
     recvMessage(PacketPtr pkt)
     {
@@ -106,27 +127,47 @@ class IntDev
         return 0;
     }
 
-    virtual void
-    getIntAddrRange(AddrRangeList &range_list)
+    virtual Tick
+    recvResponse(PacketPtr pkt)
+    {
+        return 0;
+    }
+
+    virtual AddrRangeList
+    getIntAddrRange()
     {
         panic("intAddrRange not implemented.\n");
     }
 };
 
-class IntPin : public SimObject
+class IntSinkPin : public SimObject
 {
-  protected:
+  public:
     IntDev * device;
-    int line;
+    int number;
 
-  public:
-    typedef X86IntPinParams Params;
+    typedef X86IntSinkPinParams Params;
+
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
 
-    IntDev *
-    getDevice() const
+    IntSinkPin(Params *p) : SimObject(p),
+            device(dynamic_cast<IntDev *>(p->device)), number(p->number)
     {
-        return device;
+        assert(device);
     }
+};
+
+class IntSourcePin : public SimObject
+{
+  protected:
+    std::vector<IntSinkPin *> sinks;
+
+  public:
+    typedef X86IntSourcePinParams Params;
 
     const Params *
     params() const
@@ -134,19 +175,55 @@ class IntPin : public SimObject
         return dynamic_cast<const Params *>(_params);
     }
 
-    IntPin(Params *p) : SimObject(p),
-            device(dynamic_cast<IntDev *>(p->device)), line(p->line)
+    void
+    addSink(IntSinkPin *sink)
     {
-        assert(device);
+        sinks.push_back(sink);
     }
 
     void
-    signalInterrupt()
+    raise()
+    {
+        for (int i = 0; i < sinks.size(); i++) {
+            const IntSinkPin &pin = *sinks[i];
+            pin.device->raiseInterruptPin(pin.number);
+        }
+    }
+    
+    void
+    lower()
+    {
+        for (int i = 0; i < sinks.size(); i++) {
+            const IntSinkPin &pin = *sinks[i];
+            pin.device->lowerInterruptPin(pin.number);
+        }
+    }
+
+    IntSourcePin(Params *p) : SimObject(p)
+    {}
+};
+
+class IntLine : public SimObject
+{
+  protected:
+    IntSourcePin *source;
+    IntSinkPin *sink;
+
+  public:
+    typedef X86IntLineParams Params;
+
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
+
+    IntLine(Params *p) : SimObject(p), source(p->source), sink(p->sink)
     {
-        device->signalInterrupt(line);
+        source->addSink(sink);
     }
 };
 
-}; // namespace X86ISA
+} // namespace X86ISA
 
 #endif //__DEV_X86_INTDEV_HH__