reorg instr test issue

[soc.git] / src / experiment / score6600.py

diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py
index 0d334ec1d34b1cfacee40b4dbfd9fd6aeb9cc0bd..591fb794e7f59bf565664c7d3d6fb22928f3fda6 100644 (file)
--- a/src/experiment/score6600.py
+++ b/src/experiment/score6600.py
@@ -122,12 +122,12 @@ class FunctionUnits(Elaboratable):
         m.d.comb += self.g_int_rd_pend_o.eq(intregdeps.rd_pend_o)
         m.d.comb += self.g_int_wr_pend_o.eq(intregdeps.wr_pend_o)
 
-        m.d.sync += intfudeps.rd_pend_i.eq(self.g_int_rd_pend_o)
-        m.d.sync += intfudeps.wr_pend_i.eq(self.g_int_wr_pend_o)
+        m.d.comb += intfudeps.rd_pend_i.eq(self.g_int_rd_pend_o)
+        m.d.comb += intfudeps.wr_pend_i.eq(self.g_int_wr_pend_o)
 
-        m.d.comb += intfudeps.issue_i.eq(self.fn_issue_i)
-        m.d.comb += intfudeps.go_rd_i.eq(self.go_rd_i)
-        m.d.comb += intfudeps.go_wr_i.eq(self.go_wr_i)
+        m.d.sync += intfudeps.issue_i.eq(self.fn_issue_i)
+        m.d.sync += intfudeps.go_rd_i.eq(self.go_rd_i)
+        m.d.sync += intfudeps.go_wr_i.eq(self.go_wr_i)
         m.d.comb += self.readable_o.eq(intfudeps.readable_o)
         m.d.comb += self.writable_o.eq(intfudeps.writable_o)
 
@@ -253,11 +253,12 @@ class Scoreboard(Elaboratable):
 
         # Connect Picker
         #---------
+        m.d.sync += intpick1.go_rd_i[0:2].eq(~go_rd_i[0:2])
         m.d.comb += intpick1.req_rel_i[0:2].eq(cu.req_rel_o[0:2])
         int_readable_o = intfus.readable_o
         int_writable_o = intfus.writable_o
-        m.d.sync += intpick1.readable_i[0:2].eq(int_readable_o[0:2])
-        m.d.sync += intpick1.writable_i[0:2].eq(int_writable_o[0:2])
+        m.d.comb += intpick1.readable_i[0:2].eq(int_readable_o[0:2])
+        m.d.comb += intpick1.writable_i[0:2].eq(int_writable_o[0:2])
 
         #---------
         # Connect Register File(s)
@@ -359,51 +360,51 @@ def scoreboard_sim(dut, alusim):
         yield dut.intregs.regs[i].reg.eq(i*2)
         alusim.setval(i, i*2)
 
+    yield
+
+    instrs = []
     if False:
-        yield from int_instr(dut, alusim, IADD, 4, 3, 5)
-        yield from print_reg(dut, [3,4,5])
-        yield
-        yield from int_instr(dut, alusim, IADD, 5, 2, 5)
-        yield from print_reg(dut, [3,4,5])
-        yield
-        yield from int_instr(dut, alusim, ISUB, 5, 1, 3)
-        yield from print_reg(dut, [3,4,5])
-        yield
-        for i in range(len(dut.int_insn_i)):
-            yield dut.int_insn_i[i].eq(0)
-        yield from print_reg(dut, [3,4,5])
-        yield
-        yield from print_reg(dut, [3,4,5])
-        yield
-        yield from print_reg(dut, [3,4,5])
-        yield
+        for i in range(2):
+            src1 = randint(1, dut.n_regs-1)
+            src2 = randint(1, dut.n_regs-1)
+            while True:
+                dest = randint(1, dut.n_regs-1)
+                break
+                if dest not in [src1, src2]:
+                    break
+            #src1 = 2
+            #src2 = 3
+            #dest = 2
 
-        yield from alusim.check(dut)
+            op = randint(0, 1)
+            op = i % 2
+        instrs.append((src1, src2, dest, op))
 
-    for i in range(5):
-        src1 = randint(1, dut.n_regs-1)
-        src2 = randint(1, dut.n_regs-1)
-        while True:
-            dest = randint(1, dut.n_regs-1)
-            break
-            if dest not in [src1, src2]:
-                break
-        #src1 = 7
-        #src2 = 4
-        #dest = 2
+    if False:
+        instrs.append((2, 3, 3, 0))
+        instrs.append((5, 3, 3, 1))
+
+    if True:
+        instrs.append((7, 2, 6, 1))
+        instrs.append((3, 7, 1, 1))
+        instrs.append((2, 2, 3, 1))
+
+    for i, (src1, src2, dest, op) in enumerate(instrs):
 
-        op = randint(0, 1)
-        op = 0
-        print ("random %d: %d %d %d %d\n" % (i, op, src1, src2, dest))
+        print ("instr %d: %d %d %d %d\n" % (i, op, src1, src2, dest))
         yield from int_instr(dut, alusim, op, src1, src2, dest)
         yield from print_reg(dut, [3,4,5])
-        yield
-        yield from print_reg(dut, [3,4,5])
-        for i in range(len(dut.int_insn_i)):
-            yield dut.int_insn_i[i].eq(0)
-        yield
-        yield
-
+        while True:
+            yield
+            issue_o = yield dut.issue_o
+            if issue_o:
+                yield from print_reg(dut, [3,4,5])
+                for i in range(len(dut.int_insn_i)):
+                    yield dut.int_insn_i[i].eq(0)
+                break
+            print ("busy",)
+            yield from print_reg(dut, [3,4,5])
+            yield
 
     yield
     yield from print_reg(dut, [3,4,5])