freedreno/ir3: Fix disasm of register offsets in ldp/stp.

[mesa.git] / src / freedreno / Makefile.sources

diff --git a/src/freedreno/Makefile.sources b/src/freedreno/Makefile.sources
index f6e28520acd60d15e683e7760f07cb070fe5e74c..99d9ace4a73fa864cb7d8b14493c7bafe8f19c7d 100644 (file)
--- a/src/freedreno/Makefile.sources
+++ b/src/freedreno/Makefile.sources
@@ -15,18 +15,27 @@ drm_SOURCES := \
        drm/msm_ringbuffer.c
 
 ir3_SOURCES := \
+       fdl/fd5_layout.c \
+       fdl/fd6_layout.c \
+       fdl/freedreno_layout.c \
        ir3/disasm-a3xx.c \
        ir3/instr-a3xx.h \
        ir3/ir3.c \
        ir3/ir3_a4xx.c \
        ir3/ir3_a6xx.c \
+       ir3/ir3_assembler.c \
+       ir3/ir3_assembler.h \
        ir3/ir3_compiler.c \
        ir3/ir3_compiler.h \
        ir3/ir3_compiler_nir.c \
        ir3/ir3_context.c \
        ir3/ir3_context.h \
        ir3/ir3_cp.c \
-       ir3/ir3_depth.c \
+       ir3/ir3_cp_postsched.c \
+       ir3/ir3_cf.c \
+       ir3/ir3_dce.c \
+       ir3/ir3_delay.c \
+       ir3/ir3_disk_cache.c \
        ir3/ir3_group.c \
        ir3/ir3_image.c \
        ir3/ir3_image.h \
@@ -42,16 +51,22 @@ ir3_SOURCES := \
        ir3/ir3_nir_lower_tex_prefetch.c \
        ir3/ir3_nir_lower_tg4_to_tex.c \
        ir3/ir3_nir_move_varying_inputs.c \
+       ir3/ir3_postsched.c \
        ir3/ir3_print.c \
        ir3/ir3_ra.c \
+       ir3/ir3_ra.h \
+       ir3/ir3_ra_regset.c \
        ir3/ir3_sched.c \
        ir3/ir3_shader.c \
        ir3/ir3_shader.h \
-       ir3/ir3_sun.c
+       ir3/ir3_validate.c
 
 ir3_GENERATED_FILES := \
+       ir3/ir3_lexer.c \
        ir3/ir3_nir_trig.c \
-       ir3/ir3_nir_imul.c
+       ir3/ir3_nir_imul.c \
+       ir3/ir3_parser.c \
+       ir3/ir3_parser.h
 
 perfcntrs_SOURCES := \
        perfcntrs/fd2_perfcntr.c \