freedreno/a6xx: Add multiview registers

[mesa.git] / src / freedreno / drm / msm_priv.h

diff --git a/src/freedreno/drm/msm_priv.h b/src/freedreno/drm/msm_priv.h
index acf22bcb6f8bd83069a8518a79edf9fb144f35b4..37adb13624ca793af6eb117ac8a6be221ff4c60a 100644 (file)
--- a/src/freedreno/drm/msm_priv.h
+++ b/src/freedreno/drm/msm_priv.h
@@ -29,6 +29,8 @@
 
 #include "freedreno_priv.h"
 
+#include "util/slab.h"
+
 #ifndef __user
 #  define __user
 #endif
@@ -51,6 +53,7 @@ struct msm_pipe {
        uint32_t gmem;
        uint32_t chip_id;
        uint32_t queue_id;
+       struct slab_parent_pool ring_pool;
 };
 FD_DEFINE_CAST(fd_pipe, msm_pipe);
 
@@ -63,14 +66,13 @@ struct fd_ringbuffer * msm_ringbuffer_sp_new_object(struct fd_pipe *pipe, uint32
 struct fd_submit * msm_submit_new(struct fd_pipe *pipe);
 struct fd_submit * msm_submit_sp_new(struct fd_pipe *pipe);
 
+void msm_pipe_sp_ringpool_init(struct msm_pipe *msm_pipe);
+void msm_pipe_sp_ringpool_fini(struct msm_pipe *msm_pipe);
+
+
 struct msm_bo {
        struct fd_bo base;
        uint64_t offset;
-       /* to avoid excess hashtable lookups, cache the ring this bo was
-        * last emitted on (since that will probably also be the next ring
-        * it is emitted on)
-        */
-       unsigned current_submit_seqno;
        uint32_t idx;
 };
 FD_DEFINE_CAST(fd_bo, msm_bo);
@@ -106,10 +108,9 @@ msm_dump_submit(struct drm_msm_gem_submit *req)
 static inline void get_abs_timeout(struct drm_msm_timespec *tv, uint64_t ns)
 {
        struct timespec t;
-       uint32_t s = ns / 1000000000;
        clock_gettime(CLOCK_MONOTONIC, &t);
-       tv->tv_sec = t.tv_sec + s;
-       tv->tv_nsec = t.tv_nsec + ns - (s * 1000000000);
+       tv->tv_sec = t.tv_sec + ns / 1000000000;
+       tv->tv_nsec = t.tv_nsec + ns % 1000000000;
 }
 
 /*
@@ -138,4 +139,6 @@ grow(void *ptr, uint16_t nr, uint16_t *max, uint16_t sz)
        (x)->nr_ ## name ++; \
 })
 
+#define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
+
 #endif /* MSM_PRIV_H_ */