#include "freedreno_layout.h"
-/* indexed by cpp, including msaa 2x and 4x: */
+/* indexed by cpp, including msaa 2x and 4x:
+ * TODO:
+ * cpp=1 UBWC needs testing at larger texture sizes
+ * missing UBWC blockwidth/blockheight for npot+64 cpp
+ * missing 96/128 CPP for 8x MSAA with 32_32_32/32_32_32_32
+ */
static const struct {
unsigned pitchalign;
unsigned heightalign;
+ uint8_t ubwc_blockwidth;
+ uint8_t ubwc_blockheight;
} tile_alignment[] = {
- [1] = { 128, 32 },
- [2] = { 64, 32 },
+ [1] = { 128, 32, 16, 4 },
+ [2] = { 128, 16, 16, 4 },
[3] = { 64, 32 },
- [4] = { 64, 16 },
+ [4] = { 64, 16, 16, 4 },
[6] = { 64, 16 },
- [8] = { 64, 16 },
+ [8] = { 64, 16, 8, 4, },
[12] = { 64, 16 },
- [16] = { 64, 16 },
+ [16] = { 64, 16, 4, 4, },
[24] = { 64, 16 },
- [32] = { 64, 16 },
+ [32] = { 64, 16, 4, 2 },
[48] = { 64, 16 },
[64] = { 64, 16 },
- /* special cases for r16: */
- [0] = { 128, 16 },
+ /* special cases for r8g8: */
+ [0] = { 64, 32, 16, 4 },
};
+#define RGB_TILE_WIDTH_ALIGNMENT 64
+#define RGB_TILE_HEIGHT_ALIGNMENT 16
+#define UBWC_PLANE_SIZE_ALIGNMENT 4096
+
/* NOTE: good way to test this is: (for example)
* piglit/bin/texelFetch fs sampler3D 100x100x8
*/
fdl6_layout(struct fdl_layout *layout,
enum pipe_format format, uint32_t nr_samples,
uint32_t width0, uint32_t height0, uint32_t depth0,
- uint32_t mip_levels, uint32_t array_size, bool is_3d)
+ uint32_t mip_levels, uint32_t array_size, bool is_3d, bool ubwc)
{
assert(nr_samples > 0);
layout->width0 = width0;
layout->cpp = util_format_get_blocksize(format);
layout->cpp *= nr_samples;
+ layout->format = format;
+ layout->nr_samples = nr_samples;
const struct util_format_description *format_desc =
util_format_description(format);
- uint32_t level;
uint32_t depth = depth0;
/* linear dimensions: */
uint32_t lwidth = width0;
int ta = layout->cpp;
/* The z16/r16 formats seem to not play by the normal tiling rules: */
- if ((layout->cpp == 2) && (util_format_get_nr_components(format) == 1))
+ if ((layout->cpp == 2) && (util_format_get_nr_components(format) == 2))
ta = 0;
uint32_t alignment;
debug_assert(ta < ARRAY_SIZE(tile_alignment));
debug_assert(tile_alignment[ta].pitchalign);
- for (level = 0; level < mip_levels; level++) {
+ for (uint32_t level = 0; level < mip_levels; level++) {
struct fdl_slice *slice = &layout->slices[level];
- uint32_t tile_mode = fdl_tile_mode(layout, level);
+ struct fdl_slice *ubwc_slice = &layout->ubwc_slices[level];
+ uint32_t tile_mode = (ubwc ?
+ layout->tile_mode : fdl_tile_mode(layout, level));
uint32_t width, height;
/* tiled levels of 3D textures are rounded up to PoT dimensions: */
layout->size += slice->size0 * depth * layers_in_level;
- if (false) {
- fprintf(stderr, "%s: %ux%ux%u@%u:\t%2u: stride=%4u, size=%6u,%7u, aligned_height=%3u, blocks=%u, offset=0x%x tiling=%d\n",
- util_format_name(format),
- width, height, depth, layout->cpp,
- level, slice->pitch * layout->cpp,
- slice->size0, layout->size, aligned_height, blocks,
- slice->offset, tile_mode);
+ if (ubwc) {
+ /* with UBWC every level is aligned to 4K */
+ layout->size = align(layout->size, 4096);
+
+ uint32_t block_width = tile_alignment[ta].ubwc_blockwidth;
+ uint32_t block_height = tile_alignment[ta].ubwc_blockheight;
+ uint32_t meta_pitch = align(DIV_ROUND_UP(width, block_width),
+ RGB_TILE_WIDTH_ALIGNMENT);
+ uint32_t meta_height = align(DIV_ROUND_UP(height, block_height),
+ RGB_TILE_HEIGHT_ALIGNMENT);
+
+ /* it looks like mipmaps need alignment to power of two
+ * TODO: needs testing with large npot textures
+ * (needed for the first level?)
+ */
+ if (mip_levels > 1) {
+ meta_pitch = util_next_power_of_two(meta_pitch);
+ meta_height = util_next_power_of_two(meta_height);
+ }
+
+ ubwc_slice->size0 = align(meta_pitch * meta_height, UBWC_PLANE_SIZE_ALIGNMENT);
+ ubwc_slice->pitch = meta_pitch;
+ ubwc_slice->offset = layout->ubwc_layer_size;
+ layout->ubwc_layer_size += ubwc_slice->size0;
}
depth = u_minify(depth, 1);
layout->layer_size = align(layout->size, 4096);
layout->size = layout->layer_size * array_size;
}
+
+ /* Place the UBWC slices before the uncompressed slices, because the
+ * kernel expects UBWC to be at the start of the buffer. In the HW, we
+ * get to program the UBWC and non-UBWC offset/strides
+ * independently.
+ */
+ if (ubwc) {
+ for (uint32_t level = 0; level < mip_levels; level++)
+ layout->slices[level].offset += layout->ubwc_layer_size * array_size;
+ layout->size += layout->ubwc_layer_size * array_size;
+ }
+}
+
+void
+fdl6_get_ubwc_blockwidth(struct fdl_layout *layout,
+ uint32_t *blockwidth, uint32_t *blockheight)
+{
+ *blockwidth = tile_alignment[layout->cpp].ubwc_blockwidth;
+ *blockheight = tile_alignment[layout->cpp].ubwc_blockheight;
}
projects / mesa.git / blobdiff