#include "compiler/shader_enums.h"
-#include "util/u_debug.h"
+#include "util/bitscan.h"
#include "util/list.h"
+#include "util/u_debug.h"
#include "instr-a3xx.h"
IR3_INSTR_MARK = 0x1000,
IR3_INSTR_UNUSED= 0x2000,
} flags;
- int repeat;
+ uint8_t repeat;
+ uint8_t nop;
#ifdef DEBUG
unsigned regs_max;
#endif
int src_offset;
int dst_offset;
int iim_val : 3; /* for ldgb/stgb, # of components */
- int d : 3;
+ unsigned d : 3;
bool typed : 1;
} cat6;
struct {
*/
void *data;
+ int sun; /* Sethi–Ullman number, used by sched */
+ int use_count; /* currently just updated/used by cp */
+
/* Used during CP and RA stages. For fanin and shader inputs/
* outputs where we need a sequence of consecutive registers,
* keep track of each src instructions left (ie 'n-1') and right
/* Entry in ir3_block's instruction list: */
struct list_head node;
- int use_count; /* currently just updated/used by cp */
-
#ifdef DEBUG
uint32_t serialno;
#endif
/* List of ir3_array's: */
struct list_head array_list;
+ unsigned max_sun; /* max Sethi–Ullman number */
+
#ifdef DEBUG
unsigned block_count, instr_count;
#endif
return (opc_cat(instr->opc) == -1);
}
+static inline unsigned dest_regs(struct ir3_instruction *instr)
+{
+ if ((instr->regs_count == 0) || is_store(instr))
+ return 0;
+
+ return util_last_bit(instr->regs[0]->wrmask);
+}
+
static inline bool writes_addr(struct ir3_instruction *instr)
{
if (instr->regs_count > 0) {
/* group neighbors and insert mov's to resolve conflicts: */
void ir3_group(struct ir3 *ir);
+/* Sethi–Ullman numbering: */
+void ir3_sun(struct ir3 *ir);
+
/* scheduling: */
void ir3_sched_add_deps(struct ir3 *ir);
int ir3_sched(struct ir3 *ir);
sam = ir3_instr_create(block, opc);
sam->flags |= flags;
ir3_reg_create(sam, 0, 0)->wrmask = wrmask;
+ // temporary step, extra dummy src which will become the
+ // hvec2(samp, tex) argument:
+ ir3_reg_create(sam, 0, 0);
if (src0) {
reg = ir3_reg_create(sam, 0, IR3_REG_SSA);
reg->wrmask = (1 << (src0->regs_count - 1)) - 1;