freedreno/ir3: add generic get_barycentric()

[mesa.git] / src / freedreno / ir3 / ir3.h

diff --git a/src/freedreno/ir3/ir3.h b/src/freedreno/ir3/ir3.h
index 39056b47a250296c738a76a10b9364e0de9ca513..51315a5f361530e40373190de70d1dc0dbfa757d 100644 (file)
--- a/src/freedreno/ir3/ir3.h
+++ b/src/freedreno/ir3/ir3.h
@@ -44,7 +44,7 @@ struct ir3_instruction;
 struct ir3_block;
 
 struct ir3_info {
-       uint32_t gpu_id;
+       void *data;              /* used internally in ir3 assembler */
        uint16_t sizedwords;
        uint16_t instrs_count;   /* expanded to account for rpt's */
        uint16_t nops_count;     /* # of nop instructions, including nopN */
@@ -121,9 +121,7 @@ struct ir3_register {
         * Note the size field isn't important for relative const (since
         * we don't have to do register allocation for constants).
         */
-       unsigned size : 15;
-
-       bool merged : 1;    /* half-regs conflict with full regs (ie >= a6xx) */
+       unsigned size : 16;
 
        /* normal registers:
         * the component is in the low two bits of the reg #, so
@@ -556,10 +554,12 @@ block_id(struct ir3_block *block)
 #endif
 }
 
-struct ir3 * ir3_create(struct ir3_compiler *compiler, gl_shader_stage type);
+struct ir3_shader_variant;
+
+struct ir3 * ir3_create(struct ir3_compiler *compiler, struct ir3_shader_variant *v);
 void ir3_destroy(struct ir3 *shader);
-void * ir3_assemble(struct ir3 *shader,
-               struct ir3_info *info, uint32_t gpu_id);
+
+void * ir3_assemble(struct ir3_shader_variant *v);
 void * ir3_alloc(struct ir3 *shader, int sz);
 
 struct ir3_block * ir3_block_create(struct ir3 *shader);
@@ -1314,12 +1314,12 @@ bool ir3_sched_add_deps(struct ir3 *ir);
 int ir3_sched(struct ir3 *ir);
 
 struct ir3_context;
-bool ir3_postsched(struct ir3 *ir);
+bool ir3_postsched(struct ir3 *ir, struct ir3_shader_variant *v);
 
 bool ir3_a6xx_fixup_atomic_dests(struct ir3 *ir, struct ir3_shader_variant *so);
 
 /* register assignment: */
-struct ir3_ra_reg_set * ir3_ra_alloc_reg_set(struct ir3_compiler *compiler);
+struct ir3_ra_reg_set * ir3_ra_alloc_reg_set(struct ir3_compiler *compiler, bool mergedregs);
 int ir3_ra(struct ir3_shader_variant *v, struct ir3_instruction **precolor, unsigned nprecolor);
 
 /* legalize: */
@@ -1760,21 +1760,27 @@ INSTR0(META_TEX_PREFETCH);
 
 #define MAX_REG 256
 
-typedef BITSET_DECLARE(regmask_t, 2 * MAX_REG);
+typedef BITSET_DECLARE(regmaskstate_t, 2 * MAX_REG);
+
+typedef struct {
+       bool mergedregs;
+       regmaskstate_t mask;
+} regmask_t;
 
 static inline bool
 __regmask_get(regmask_t *regmask, struct ir3_register *reg, unsigned n)
 {
-       if (reg->merged) {
+       if (regmask->mergedregs) {
                /* a6xx+ case, with merged register file, we track things in terms
                 * of half-precision registers, with a full precisions register
                 * using two half-precision slots:
                 */
                if (reg->flags & IR3_REG_HALF) {
-                       return BITSET_TEST(*regmask, n);
+                       return BITSET_TEST(regmask->mask, n);
                } else {
                        n *= 2;
-                       return BITSET_TEST(*regmask, n) || BITSET_TEST(*regmask, n+1);
+                       return BITSET_TEST(regmask->mask, n) ||
+                               BITSET_TEST(regmask->mask, n+1);
                }
        } else {
                /* pre a6xx case, with separate register file for half and full
@@ -1782,24 +1788,24 @@ __regmask_get(regmask_t *regmask, struct ir3_register *reg, unsigned n)
                 */
                if (reg->flags & IR3_REG_HALF)
                        n += MAX_REG;
-               return BITSET_TEST(*regmask, n);
+               return BITSET_TEST(regmask->mask, n);
        }
 }
 
 static inline void
 __regmask_set(regmask_t *regmask, struct ir3_register *reg, unsigned n)
 {
-       if (reg->merged) {
+       if (regmask->mergedregs) {
                /* a6xx+ case, with merged register file, we track things in terms
                 * of half-precision registers, with a full precisions register
                 * using two half-precision slots:
                 */
                if (reg->flags & IR3_REG_HALF) {
-                       BITSET_SET(*regmask, n);
+                       BITSET_SET(regmask->mask, n);
                } else {
                        n *= 2;
-                       BITSET_SET(*regmask, n);
-                       BITSET_SET(*regmask, n+1);
+                       BITSET_SET(regmask->mask, n);
+                       BITSET_SET(regmask->mask, n+1);
                }
        } else {
                /* pre a6xx case, with separate register file for half and full
@@ -1807,13 +1813,14 @@ __regmask_set(regmask_t *regmask, struct ir3_register *reg, unsigned n)
                 */
                if (reg->flags & IR3_REG_HALF)
                        n += MAX_REG;
-               BITSET_SET(*regmask, n);
+               BITSET_SET(regmask->mask, n);
        }
 }
 
-static inline void regmask_init(regmask_t *regmask)
+static inline void regmask_init(regmask_t *regmask, bool mergedregs)
 {
-       memset(regmask, 0, sizeof(*regmask));
+       memset(&regmask->mask, 0, sizeof(regmask->mask));
+       regmask->mergedregs = mergedregs;
 }
 
 static inline void regmask_set(regmask_t *regmask, struct ir3_register *reg)
@@ -1830,9 +1837,11 @@ static inline void regmask_set(regmask_t *regmask, struct ir3_register *reg)
 
 static inline void regmask_or(regmask_t *dst, regmask_t *a, regmask_t *b)
 {
-       unsigned i;
-       for (i = 0; i < ARRAY_SIZE(*dst); i++)
-               (*dst)[i] = (*a)[i] | (*b)[i];
+       assert(dst->mergedregs == a->mergedregs);
+       assert(dst->mergedregs == b->mergedregs);
+
+       for (unsigned i = 0; i < ARRAY_SIZE(dst->mask); i++)
+               dst->mask[i] = a->mask[i] | b->mask[i];
 }
 
 static inline bool regmask_get(regmask_t *regmask,