freedreno/ir3: handle half registers for arrays during register allocation.

[mesa.git] / src / freedreno / ir3 / ir3.h

diff --git a/src/freedreno/ir3/ir3.h b/src/freedreno/ir3/ir3.h
index ac2949341338759e62b9d9c4c8b750913b6f6a70..f927d1ff2045a991e8457c512bc4bb658b2b2870 100644 (file)
--- a/src/freedreno/ir3/ir3.h
+++ b/src/freedreno/ir3/ir3.h
@@ -500,6 +500,9 @@ struct ir3_array {
        unsigned base;      /* base vreg name */
        unsigned reg;       /* base physical reg */
        uint16_t start_ip, end_ip;
+
+       /* Indicates if half-precision */
+       bool half;
 };
 
 struct ir3_array * ir3_lookup_array(struct ir3 *ir, unsigned id);
@@ -695,6 +698,25 @@ static inline bool is_same_type_mov(struct ir3_instruction *instr)
        return true;
 }
 
+/* A move from const, which changes size but not type, can also be
+ * folded into dest instruction in some cases.
+ */
+static inline bool is_const_mov(struct ir3_instruction *instr)
+{
+       if (instr->opc != OPC_MOV)
+               return false;
+
+       if (!(instr->regs[1]->flags & IR3_REG_CONST))
+               return false;
+
+       type_t src_type = instr->cat1.src_type;
+       type_t dst_type = instr->cat1.dst_type;
+
+       return (type_float(src_type) && type_float(dst_type)) ||
+               (type_uint(src_type) && type_uint(dst_type)) ||
+               (type_sint(src_type) && type_sint(dst_type));
+}
+
 static inline bool is_alu(struct ir3_instruction *instr)
 {
        return (1 <= opc_cat(instr->opc)) && (opc_cat(instr->opc) <= 3);
@@ -710,6 +732,11 @@ static inline bool is_tex(struct ir3_instruction *instr)
        return (opc_cat(instr->opc) == 5);
 }
 
+static inline bool is_tex_or_prefetch(struct ir3_instruction *instr)
+{
+       return is_tex(instr) || (instr->opc == OPC_META_TEX_PREFETCH);
+}
+
 static inline bool is_mem(struct ir3_instruction *instr)
 {
        return (opc_cat(instr->opc) == 6);
@@ -794,7 +821,7 @@ static inline bool is_meta(struct ir3_instruction *instr)
 
 static inline unsigned dest_regs(struct ir3_instruction *instr)
 {
-       if ((instr->regs_count == 0) || is_store(instr))
+       if ((instr->regs_count == 0) || is_store(instr) || is_flow(instr))
                return 0;
 
        return util_last_bit(instr->regs[0]->wrmask);
@@ -1116,8 +1143,6 @@ void ir3_print_instr(struct ir3_instruction *instr);
 /* delay calculation: */
 int ir3_delayslots(struct ir3_instruction *assigner,
                struct ir3_instruction *consumer, unsigned n);
-unsigned ir3_distance(struct ir3_block *block, struct ir3_instruction *instr,
-               unsigned maxd, bool pred);
 unsigned ir3_delay_calc(struct ir3_block *block, struct ir3_instruction *instr,
                bool soft, bool pred);
 void ir3_remove_nops(struct ir3 *ir);
@@ -1127,6 +1152,9 @@ struct ir3_shader_variant;
 void ir3_insert_by_depth(struct ir3_instruction *instr, struct list_head *list);
 void ir3_depth(struct ir3 *ir, struct ir3_shader_variant *so);
 
+/* fp16 conversion folding */
+void ir3_cf(struct ir3 *ir);
+
 /* copy-propagate: */
 void ir3_cp(struct ir3 *ir, struct ir3_shader_variant *so);
 
@@ -1140,7 +1168,10 @@ void ir3_sun(struct ir3 *ir);
 void ir3_sched_add_deps(struct ir3 *ir);
 int ir3_sched(struct ir3 *ir);
 
-void ir3_a6xx_fixup_atomic_dests(struct ir3 *ir, struct ir3_shader_variant *so);
+struct ir3_context;
+int ir3_postsched(struct ir3_context *ctx);
+
+bool ir3_a6xx_fixup_atomic_dests(struct ir3 *ir, struct ir3_shader_variant *so);
 
 /* register assignment: */
 struct ir3_ra_reg_set * ir3_ra_alloc_reg_set(struct ir3_compiler *compiler);
@@ -1182,7 +1213,7 @@ create_immed_typed(struct ir3_block *block, uint32_t val, type_t type)
        mov->cat1.src_type = type;
        mov->cat1.dst_type = type;
        __ssa_dst(mov)->flags |= flags;
-       ir3_reg_create(mov, 0, IR3_REG_IMMED)->uim_val = val;
+       ir3_reg_create(mov, 0, IR3_REG_IMMED | flags)->uim_val = val;
 
        return mov;
 }
@@ -1359,7 +1390,7 @@ ir3_##name(struct ir3_block *block,                                      \
 #define INSTR4(name)        __INSTR4(0, name, OPC_##name)
 
 /* cat0 instructions: */
-INSTR0(BR)
+INSTR1(BR)
 INSTR0(JUMP)
 INSTR1(KILL)
 INSTR0(END)
@@ -1438,8 +1469,11 @@ INSTR3(SAD_S32)
 /* cat4 instructions: */
 INSTR1(RCP)
 INSTR1(RSQ)
+INSTR1(HRSQ)
 INSTR1(LOG2)
+INSTR1(HLOG2)
 INSTR1(EXP2)
+INSTR1(HEXP2)
 INSTR1(SIN)
 INSTR1(COS)
 INSTR1(SQRT)