ir3: Fix LDC offset units

[mesa.git] / src / freedreno / ir3 / ir3_compiler.c

diff --git a/src/freedreno/ir3/ir3_compiler.c b/src/freedreno/ir3/ir3_compiler.c
index be9ae83b27815b26e226fea3afe2526b9c6f829d..3bb71c8942de35b68bf36ac927e458a85b53337d 100644 (file)
--- a/src/freedreno/ir3/ir3_compiler.c
+++ b/src/freedreno/ir3/ir3_compiler.c
@@ -30,12 +30,21 @@
 
 static const struct debug_named_value shader_debug_options[] = {
        {"vs",         IR3_DBG_SHADER_VS,  "Print shader disasm for vertex shaders"},
+       {"tcs",        IR3_DBG_SHADER_TCS, "Print shader disasm for tess ctrl shaders"},
+       {"tes",        IR3_DBG_SHADER_TES, "Print shader disasm for tess eval shaders"},
+       {"gs",         IR3_DBG_SHADER_GS,  "Print shader disasm for geometry shaders"},
        {"fs",         IR3_DBG_SHADER_FS,  "Print shader disasm for fragment shaders"},
        {"cs",         IR3_DBG_SHADER_CS,  "Print shader disasm for compute shaders"},
        {"disasm",     IR3_DBG_DISASM,     "Dump NIR and adreno shader disassembly"},
        {"optmsgs",    IR3_DBG_OPTMSGS,    "Enable optimizer debug messages"},
        {"forces2en",  IR3_DBG_FORCES2EN,  "Force s2en mode for tex sampler instructions"},
        {"nouboopt",   IR3_DBG_NOUBOOPT,   "Disable lowering UBO to uniform"},
+       {"nofp16",     IR3_DBG_NOFP16,     "Don't lower mediump to fp16"},
+#ifdef DEBUG
+       /* DEBUG-only options: */
+       {"schedmsgs",  IR3_DBG_SCHEDMSGS,  "Enable scheduler debug messages"},
+       {"ramsgs",     IR3_DBG_RAMSGS,     "Enable register-allocation debug messages"},
+#endif
        DEBUG_NAMED_VALUE_END
 };