static const struct debug_named_value shader_debug_options[] = {
{"vs", IR3_DBG_SHADER_VS, "Print shader disasm for vertex shaders"},
+ {"tcs", IR3_DBG_SHADER_TCS, "Print shader disasm for tess ctrl shaders"},
+ {"tes", IR3_DBG_SHADER_TES, "Print shader disasm for tess eval shaders"},
+ {"gs", IR3_DBG_SHADER_GS, "Print shader disasm for geometry shaders"},
{"fs", IR3_DBG_SHADER_FS, "Print shader disasm for fragment shaders"},
{"cs", IR3_DBG_SHADER_CS, "Print shader disasm for compute shaders"},
{"disasm", IR3_DBG_DISASM, "Dump NIR and adreno shader disassembly"},
{"optmsgs", IR3_DBG_OPTMSGS, "Enable optimizer debug messages"},
{"forces2en", IR3_DBG_FORCES2EN, "Force s2en mode for tex sampler instructions"},
{"nouboopt", IR3_DBG_NOUBOOPT, "Disable lowering UBO to uniform"},
+ {"nofp16", IR3_DBG_NOFP16, "Don't lower mediump to fp16"},
+#ifdef DEBUG
+ /* DEBUG-only options: */
+ {"schedmsgs", IR3_DBG_SCHEDMSGS, "Enable scheduler debug messages"},
+ {"ramsgs", IR3_DBG_RAMSGS, "Enable register-allocation debug messages"},
+#endif
DEBUG_NAMED_VALUE_END
};
compiler->dev = dev;
compiler->gpu_id = gpu_id;
- compiler->set = ir3_ra_alloc_reg_set(compiler);
+ compiler->set = ir3_ra_alloc_reg_set(compiler, false);
if (compiler->gpu_id >= 600) {
+ compiler->mergedregs_set = ir3_ra_alloc_reg_set(compiler, true);
compiler->samgq_workaround = true;
}
compiler->unminify_coords = false;
compiler->txf_ms_with_isaml = false;
compiler->array_index_add_half = true;
+ /* Some a6xxs can apparently do 640 consts, but not all. Need to
+ * characterize this better across GPUs
+ */
+ compiler->max_const = 512;
+ compiler->const_upload_unit = 4;
} else {
/* no special handling for "flat" */
compiler->flat_bypass = false;
compiler->unminify_coords = true;
compiler->txf_ms_with_isaml = true;
compiler->array_index_add_half = false;
+ compiler->max_const = 512;
+ compiler->const_upload_unit = 8;
}
return compiler;