freedreno/ir3: pass variant to postsched

[mesa.git] / src / freedreno / ir3 / ir3_compiler.c

diff --git a/src/freedreno/ir3/ir3_compiler.c b/src/freedreno/ir3/ir3_compiler.c
index f00daebabf5dbf19ee7960cd99421b96bca32ca9..7e74f9ba6da24b0bd6cce72b0142a5040a4d2aca 100644 (file)
--- a/src/freedreno/ir3/ir3_compiler.c
+++ b/src/freedreno/ir3/ir3_compiler.c
@@ -29,12 +29,23 @@
 #include "ir3_compiler.h"
 
 static const struct debug_named_value shader_debug_options[] = {
-               {"vs", IR3_DBG_SHADER_VS, "Print shader disasm for vertex shaders"},
-               {"fs", IR3_DBG_SHADER_FS, "Print shader disasm for fragment shaders"},
-               {"cs", IR3_DBG_SHADER_CS, "Print shader disasm for compute shaders"},
-               {"disasm",  IR3_DBG_DISASM, "Dump NIR and adreno shader disassembly"},
-               {"optmsgs", IR3_DBG_OPTMSGS,"Enable optimizer debug messages"},
-               DEBUG_NAMED_VALUE_END
+       {"vs",         IR3_DBG_SHADER_VS,  "Print shader disasm for vertex shaders"},
+       {"tcs",        IR3_DBG_SHADER_TCS, "Print shader disasm for tess ctrl shaders"},
+       {"tes",        IR3_DBG_SHADER_TES, "Print shader disasm for tess eval shaders"},
+       {"gs",         IR3_DBG_SHADER_GS,  "Print shader disasm for geometry shaders"},
+       {"fs",         IR3_DBG_SHADER_FS,  "Print shader disasm for fragment shaders"},
+       {"cs",         IR3_DBG_SHADER_CS,  "Print shader disasm for compute shaders"},
+       {"disasm",     IR3_DBG_DISASM,     "Dump NIR and adreno shader disassembly"},
+       {"optmsgs",    IR3_DBG_OPTMSGS,    "Enable optimizer debug messages"},
+       {"forces2en",  IR3_DBG_FORCES2EN,  "Force s2en mode for tex sampler instructions"},
+       {"nouboopt",   IR3_DBG_NOUBOOPT,   "Disable lowering UBO to uniform"},
+       {"nofp16",     IR3_DBG_NOFP16,     "Don't lower mediump to fp16"},
+#ifdef DEBUG
+       /* DEBUG-only options: */
+       {"schedmsgs",  IR3_DBG_SCHEDMSGS,  "Enable scheduler debug messages"},
+       {"ramsgs",     IR3_DBG_RAMSGS,     "Enable register-allocation debug messages"},
+#endif
+       DEBUG_NAMED_VALUE_END
 };
 
 DEBUG_GET_ONCE_FLAGS_OPTION(ir3_shader_debug, "IR3_SHADER_DEBUG", shader_debug_options, 0)
@@ -49,7 +60,12 @@ struct ir3_compiler * ir3_compiler_create(struct fd_device *dev, uint32_t gpu_id
 
        compiler->dev = dev;
        compiler->gpu_id = gpu_id;
-       compiler->set = ir3_ra_alloc_reg_set(compiler);
+       compiler->set = ir3_ra_alloc_reg_set(compiler, false);
+
+       if (compiler->gpu_id >= 600) {
+               compiler->mergedregs_set = ir3_ra_alloc_reg_set(compiler, true);
+               compiler->samgq_workaround = true;
+       }
 
        if (compiler->gpu_id >= 400) {
                /* need special handling for "flat" */
@@ -58,6 +74,11 @@ struct ir3_compiler * ir3_compiler_create(struct fd_device *dev, uint32_t gpu_id
                compiler->unminify_coords = false;
                compiler->txf_ms_with_isaml = false;
                compiler->array_index_add_half = true;
+               /* Some a6xxs can apparently do 640 consts, but not all.  Need to
+                * characterize this better across GPUs
+                */
+               compiler->max_const = 512;
+               compiler->const_upload_unit = 4;
        } else {
                /* no special handling for "flat" */
                compiler->flat_bypass = false;
@@ -65,6 +86,8 @@ struct ir3_compiler * ir3_compiler_create(struct fd_device *dev, uint32_t gpu_id
                compiler->unminify_coords = true;
                compiler->txf_ms_with_isaml = true;
                compiler->array_index_add_half = false;
+               compiler->max_const = 512;
+               compiler->const_upload_unit = 8;
        }
 
        return compiler;