freedreno: Only call nir_lower_io on shader_in/out

[mesa.git] / src / freedreno / ir3 / ir3_compiler.h

diff --git a/src/freedreno/ir3/ir3_compiler.h b/src/freedreno/ir3/ir3_compiler.h
index e2336062b2931d9d0e9181175fc35a8a3c338b65..54a1afd5a257ca41e75416d319eab0124f1f9108 100644 (file)
--- a/src/freedreno/ir3/ir3_compiler.h
+++ b/src/freedreno/ir3/ir3_compiler.h
@@ -27,16 +27,22 @@
 #ifndef IR3_COMPILER_H_
 #define IR3_COMPILER_H_
 
-#include "ir3_shader.h"
+#include "util/disk_cache.h"
+
+#include "ir3.h"
 
 struct ir3_ra_reg_set;
+struct ir3_shader;
 
 struct ir3_compiler {
        struct fd_device *dev;
        uint32_t gpu_id;
        struct ir3_ra_reg_set *set;
+       struct ir3_ra_reg_set *mergedregs_set;
        uint32_t shader_count;
 
+       struct disk_cache *disk_cache;
+
        /*
         * Configuration options for things that are handled differently on
         * different generations:
@@ -63,19 +69,74 @@ struct ir3_compiler {
         * index coordinate:
         */
        bool array_index_add_half;
+
+       /* on a6xx, rewrite samgp to sequence of samgq0-3 in vertex shaders:
+        */
+       bool samgq_workaround;
+
+       /* The maximum number of constants, in vec4's, across the entire graphics
+        * pipeline.
+        */
+       uint16_t max_const_pipeline;
+
+       /* The maximum number of constants, in vec4's, for VS+HS+DS+GS. */
+       uint16_t max_const_geom;
+
+       /* The maximum number of constants, in vec4's, for FS. */
+       uint16_t max_const_frag;
+
+       /* A "safe" max constlen that can be applied to each shader in the
+        * pipeline which we guarantee will never exceed any combined limits.
+        */
+       uint16_t max_const_safe;
+
+       /* The maximum number of constants, in vec4's, for compute shaders. */
+       uint16_t max_const_compute;
+
+       /* on a3xx, the unit of indirect const load is higher than later gens (in
+        * vec4 units):
+        */
+       uint32_t const_upload_unit;
 };
 
+void ir3_compiler_destroy(struct ir3_compiler *compiler);
 struct ir3_compiler * ir3_compiler_create(struct fd_device *dev, uint32_t gpu_id);
 
+void ir3_disk_cache_init(struct ir3_compiler *compiler);
+void ir3_disk_cache_init_shader_key(struct ir3_compiler *compiler,
+               struct ir3_shader *shader);
+bool ir3_disk_cache_retrieve(struct ir3_compiler *compiler,
+               struct ir3_shader_variant *v);
+void ir3_disk_cache_store(struct ir3_compiler *compiler,
+               struct ir3_shader_variant *v);
+
 int ir3_compile_shader_nir(struct ir3_compiler *compiler,
                struct ir3_shader_variant *so);
 
+/* gpu pointer size in units of 32bit registers/slots */
+static inline
+unsigned ir3_pointer_size(struct ir3_compiler *compiler)
+{
+       return (compiler->gpu_id >= 500) ? 2 : 1;
+}
+
 enum ir3_shader_debug {
-       IR3_DBG_SHADER_VS = 0x01,
-       IR3_DBG_SHADER_FS = 0x02,
-       IR3_DBG_SHADER_CS = 0x04,
-       IR3_DBG_DISASM    = 0x08,
-       IR3_DBG_OPTMSGS   = 0x10,
+       IR3_DBG_SHADER_VS  = BITFIELD_BIT(0),
+       IR3_DBG_SHADER_TCS = BITFIELD_BIT(1),
+       IR3_DBG_SHADER_TES = BITFIELD_BIT(2),
+       IR3_DBG_SHADER_GS  = BITFIELD_BIT(3),
+       IR3_DBG_SHADER_FS  = BITFIELD_BIT(4),
+       IR3_DBG_SHADER_CS  = BITFIELD_BIT(5),
+       IR3_DBG_DISASM     = BITFIELD_BIT(6),
+       IR3_DBG_OPTMSGS    = BITFIELD_BIT(7),
+       IR3_DBG_FORCES2EN  = BITFIELD_BIT(8),
+       IR3_DBG_NOUBOOPT   = BITFIELD_BIT(9),
+       IR3_DBG_NOFP16     = BITFIELD_BIT(10),
+       IR3_DBG_NOCACHE    = BITFIELD_BIT(11),
+
+       /* DEBUG-only options: */
+       IR3_DBG_SCHEDMSGS  = BITFIELD_BIT(20),
+       IR3_DBG_RAMSGS     = BITFIELD_BIT(21),
 };
 
 extern enum ir3_shader_debug ir3_shader_debug;
@@ -83,8 +144,14 @@ extern enum ir3_shader_debug ir3_shader_debug;
 static inline bool
 shader_debug_enabled(gl_shader_stage type)
 {
+       if (ir3_shader_debug & IR3_DBG_DISASM)
+               return true;
+
        switch (type) {
        case MESA_SHADER_VERTEX:      return !!(ir3_shader_debug & IR3_DBG_SHADER_VS);
+       case MESA_SHADER_TESS_CTRL:   return !!(ir3_shader_debug & IR3_DBG_SHADER_TCS);
+       case MESA_SHADER_TESS_EVAL:   return !!(ir3_shader_debug & IR3_DBG_SHADER_TES);
+       case MESA_SHADER_GEOMETRY:    return !!(ir3_shader_debug & IR3_DBG_SHADER_GS);
        case MESA_SHADER_FRAGMENT:    return !!(ir3_shader_debug & IR3_DBG_SHADER_FS);
        case MESA_SHADER_COMPUTE:     return !!(ir3_shader_debug & IR3_DBG_SHADER_CS);
        default:
@@ -93,4 +160,13 @@ shader_debug_enabled(gl_shader_stage type)
        }
 }
 
+static inline void
+ir3_debug_print(struct ir3 *ir, const char *when)
+{
+       if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
+               printf("%s:\n", when);
+               ir3_print(ir);
+       }
+}
+
 #endif /* IR3_COMPILER_H_ */