freedreno/ir3: add assert

[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c

diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c
index c6cddc0b9cac4385679fc219d65c34c8a003d605..01f0985da62adbcd0a6b226ecb40bdcf62c81b90 100644 (file)
--- a/src/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/freedreno/ir3/ir3_compiler_nir.c
@@ -1040,7 +1040,7 @@ emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
 static struct ir3_instruction *
 get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
 {
-       unsigned slot = ir3_get_image_slot(nir_src_as_deref(intr->src[0]));
+       unsigned slot = nir_src_as_uint(intr->src[0]);
        unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
        struct ir3_instruction *texture, *sampler;
 
@@ -1059,13 +1059,12 @@ emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
                struct ir3_instruction **dst)
 {
        struct ir3_block *b = ctx->block;
-       const nir_variable *var = nir_intrinsic_get_var(intr, 0);
        struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
        struct ir3_instruction *sam;
        struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
        struct ir3_instruction *coords[4];
-       unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
-       type_t type = ir3_get_image_type(var);
+       unsigned flags, ncoords = ir3_get_image_coords(intr, &flags);
+       type_t type = ir3_get_type_for_image_intrinsic(intr);
 
        /* hmm, this seems a bit odd, but it is what blob does and (at least
         * a5xx) just faults on bogus addresses otherwise:
@@ -1095,10 +1094,9 @@ emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
                struct ir3_instruction **dst)
 {
        struct ir3_block *b = ctx->block;
-       const nir_variable *var = nir_intrinsic_get_var(intr, 0);
        struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
        struct ir3_instruction *sam, *lod;
-       unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
+       unsigned flags, ncoords = ir3_get_image_coords(intr, &flags);
        type_t dst_type = nir_dest_bit_size(intr->dest) < 32 ?
                        TYPE_U16 : TYPE_U32;
 
@@ -1126,9 +1124,7 @@ emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
         *
         * TODO: This is at least true on a5xx. Check other gens.
         */
-       enum glsl_sampler_dim dim =
-               glsl_get_sampler_dim(glsl_without_array(var->type));
-       if (dim == GLSL_SAMPLER_DIM_BUF) {
+       if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF) {
                /* Since all the possible values the divisor can take are
                 * power-of-two (4, 8, or 16), the division is implemented
                 * as a shift-right.
@@ -1138,7 +1134,7 @@ emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
                 */
                struct ir3_const_state *const_state = &ctx->so->shader->const_state;
                unsigned cb = regid(const_state->offsets.image_dims, 0) +
-                       const_state->image_dims.off[var->data.driver_location];
+                       const_state->image_dims.off[nir_src_as_uint(intr->src[0])];
                struct ir3_instruction *aux = create_uniform(b, cb + 1);
 
                tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
@@ -1544,6 +1540,7 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
                                         * nir_variable to figure out what it is.
                                         */
                                        dst[i] = ctx->inputs[inloc];
+                                       compile_assert(ctx, dst[i]);
                                }
                        }
                } else {
@@ -1621,28 +1618,28 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
        case nir_intrinsic_shared_atomic_comp_swap:
                dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
                break;
-       case nir_intrinsic_image_deref_load:
+       case nir_intrinsic_image_load:
                emit_intrinsic_load_image(ctx, intr, dst);
                break;
-       case nir_intrinsic_image_deref_store:
+       case nir_intrinsic_image_store:
                if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
                                !ctx->s->info.fs.early_fragment_tests)
                        ctx->so->no_earlyz = true;
                ctx->funcs->emit_intrinsic_store_image(ctx, intr);
                break;
-       case nir_intrinsic_image_deref_size:
+       case nir_intrinsic_image_size:
                emit_intrinsic_image_size(ctx, intr, dst);
                break;
-       case nir_intrinsic_image_deref_atomic_add:
-       case nir_intrinsic_image_deref_atomic_imin:
-       case nir_intrinsic_image_deref_atomic_umin:
-       case nir_intrinsic_image_deref_atomic_imax:
-       case nir_intrinsic_image_deref_atomic_umax:
-       case nir_intrinsic_image_deref_atomic_and:
-       case nir_intrinsic_image_deref_atomic_or:
-       case nir_intrinsic_image_deref_atomic_xor:
-       case nir_intrinsic_image_deref_atomic_exchange:
-       case nir_intrinsic_image_deref_atomic_comp_swap:
+       case nir_intrinsic_image_atomic_add:
+       case nir_intrinsic_image_atomic_imin:
+       case nir_intrinsic_image_atomic_umin:
+       case nir_intrinsic_image_atomic_imax:
+       case nir_intrinsic_image_atomic_umax:
+       case nir_intrinsic_image_atomic_and:
+       case nir_intrinsic_image_atomic_or:
+       case nir_intrinsic_image_atomic_xor:
+       case nir_intrinsic_image_atomic_exchange:
+       case nir_intrinsic_image_atomic_comp_swap:
                if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
                                !ctx->s->info.fs.early_fragment_tests)
                        ctx->so->no_earlyz = true;