dst[0]->cat5.type = TYPE_F32;
break;
case nir_op_fddx_fine:
- dst[0] = ir3_DSXPP_1(b, src[0], 0);
+ dst[0] = ir3_DSXPP_MACRO(b, src[0], 0);
dst[0]->cat5.type = TYPE_F32;
break;
case nir_op_fddy:
break;
break;
case nir_op_fddy_fine:
- dst[0] = ir3_DSYPP_1(b, src[0], 0);
+ dst[0] = ir3_DSYPP_MACRO(b, src[0], 0);
dst[0]->cat5.type = TYPE_F32;
break;
case nir_op_flt:
dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
dst[0]->cat2.condition = IR3_COND_EQ;
break;
- case nir_op_fne:
+ case nir_op_fneu:
dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
dst[0]->cat2.condition = IR3_COND_NE;
break;
base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
} else {
- base_lo = create_uniform_indirect(b, ubo, ir3_get_addr0(ctx, src0, ptrsz));
- base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr0(ctx, src0, ptrsz));
+ base_lo = create_uniform_indirect(b, ubo, TYPE_U32, ir3_get_addr0(ctx, src0, ptrsz));
+ base_hi = create_uniform_indirect(b, ubo + 1, TYPE_U32, ir3_get_addr0(ctx, src0, ptrsz));
/* NOTE: since relative addressing is used, make sure constlen is
* at least big enough to cover all the UBO addresses, since the
emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
struct ir3_instruction **dst)
{
+ if (ir3_bindless_resource(intr->src[0])) {
+ struct ir3_block *b = ctx->block;
+ struct ir3_instruction *ibo = ir3_ssbo_to_ibo(ctx, intr->src[0]);
+ struct ir3_instruction *resinfo = ir3_RESINFO(b, ibo, 0);
+ resinfo->cat6.iim_val = 1;
+ resinfo->cat6.d = 1;
+ resinfo->cat6.type = TYPE_U32;
+ resinfo->cat6.typed = false;
+ /* resinfo has no writemask and always writes out 3 components */
+ resinfo->regs[0]->wrmask = MASK(3);
+ ir3_handle_bindless_cat6(resinfo, intr->src[0]);
+ struct ir3_instruction *resinfo_dst;
+ ir3_split_dest(b, &resinfo_dst, resinfo, 0, 1);
+ /* Unfortunately resinfo returns the array length, i.e. in dwords,
+ * while NIR expects us to return the size in bytes.
+ *
+ * TODO: fix this in NIR.
+ */
+ *dst = ir3_SHL_B(b, resinfo_dst, 0, create_immed(b, 2), 0);
+ return;
+ }
+
/* SSBO size stored as a const starting at ssbo_sizes: */
const struct ir3_const_state *const_state = ir3_const_state(ctx->so);
unsigned blk_idx = nir_src_as_uint(intr->src[0]);
create_immed(b, intr->num_components), 0,
create_immed(b, base), 0);
+ /* for a650, use LDL for tess ctrl inputs: */
+ if (ctx->so->type == MESA_SHADER_TESS_CTRL && ctx->compiler->tess_use_shared)
+ load->opc = OPC_LDL;
+
load->cat6.type = utype_dst(intr->dest);
load->regs[0]->wrmask = MASK(intr->num_components);
ir3_create_collect(ctx, value, intr->num_components), 0,
create_immed(b, intr->num_components), 0);
+ /* for a650, use STL for vertex outputs used by tess ctrl shader: */
+ if (ctx->so->type == MESA_SHADER_VERTEX && ctx->so->key.tessellation &&
+ ctx->compiler->tess_use_shared)
+ store->opc = OPC_STL;
+
store->cat6.dst_offset = nir_intrinsic_base(intr);
store->cat6.type = utype_src(intr->src[0]);
store->barrier_class = IR3_BARRIER_SHARED_W;
TYPE_U16 : TYPE_U32;
info.flags |= flags;
+ assert(nir_src_as_uint(intr->src[1]) == 0);
lod = create_immed(b, 0);
sam = emit_sam(ctx, OPC_GETSIZE, info, dst_type, 0b1111, lod, NULL);
return ctx->ij[bary];
}
-static struct ir3_instruction *
-get_barycentric_centroid(struct ir3_context *ctx)
+/* TODO: make this a common NIR helper?
+ * there is a nir_system_value_from_intrinsic but it takes nir_intrinsic_op so it
+ * can't be extended to work with this
+ */
+static gl_system_value
+nir_intrinsic_barycentric_sysval(nir_intrinsic_instr *intr)
{
- return get_barycentric(ctx, IJ_PERSP_CENTROID);
-}
+ enum glsl_interp_mode interp_mode = nir_intrinsic_interp_mode(intr);
+ gl_system_value sysval;
-static struct ir3_instruction *
-get_barycentric_sample(struct ir3_context *ctx)
-{
- return get_barycentric(ctx, IJ_PERSP_SAMPLE);
+ switch (intr->intrinsic) {
+ case nir_intrinsic_load_barycentric_pixel:
+ if (interp_mode == INTERP_MODE_NOPERSPECTIVE)
+ sysval = SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL;
+ else
+ sysval = SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL;
+ break;
+ case nir_intrinsic_load_barycentric_centroid:
+ if (interp_mode == INTERP_MODE_NOPERSPECTIVE)
+ sysval = SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID;
+ else
+ sysval = SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID;
+ break;
+ case nir_intrinsic_load_barycentric_sample:
+ if (interp_mode == INTERP_MODE_NOPERSPECTIVE)
+ sysval = SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE;
+ else
+ sysval = SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE;
+ break;
+ default:
+ unreachable("invalid barycentric intrinsic");
+ }
+
+ return sysval;
}
-static struct ir3_instruction *
-get_barycentric_pixel(struct ir3_context *ctx)
+static void
+emit_intrinsic_barycentric(struct ir3_context *ctx, nir_intrinsic_instr *intr,
+ struct ir3_instruction **dst)
{
- return get_barycentric(ctx, IJ_PERSP_PIXEL);
+ gl_system_value sysval = nir_intrinsic_barycentric_sysval(intr);
+
+ if (!ctx->so->key.msaa) {
+ if (sysval == SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE)
+ sysval = SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL;
+ if (sysval == SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE)
+ sysval = SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL;
+ }
+
+ enum ir3_bary bary = sysval - SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL;
+
+ struct ir3_instruction *ij = get_barycentric(ctx, bary);
+ ir3_split_dest(ctx->block, dst, ij, 0, 2);
}
static struct ir3_instruction *
src = ir3_get_src(ctx, &intr->src[0]);
for (int i = 0; i < dest_components; i++) {
dst[i] = create_uniform_indirect(b, idx + i,
+ nir_dest_bit_size(intr->dest) == 16 ? TYPE_F16 : TYPE_F32,
ir3_get_addr0(ctx, src[0], 1));
}
/* NOTE: if relative addressing is used, we set
dst[0] = ctx->ij[IJ_PERSP_SIZE];
break;
case nir_intrinsic_load_barycentric_centroid:
- ir3_split_dest(b, dst, get_barycentric_centroid(ctx), 0, 2);
- break;
case nir_intrinsic_load_barycentric_sample:
- if (ctx->so->key.msaa) {
- ir3_split_dest(b, dst, get_barycentric_sample(ctx), 0, 2);
- } else {
- ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
- }
- break;
case nir_intrinsic_load_barycentric_pixel:
- ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
+ emit_intrinsic_barycentric(ctx, intr, dst);
break;
case nir_intrinsic_load_interpolated_input:
idx = nir_intrinsic_base(intr);
}
dst[0] = ctx->base_instance;
break;
+ case nir_intrinsic_load_view_index:
+ if (!ctx->view_index) {
+ ctx->view_index = create_sysval_input(ctx, SYSTEM_VALUE_VIEW_INDEX, 0x1);
+ }
+ dst[0] = ctx->view_index;
+ break;
case nir_intrinsic_load_vertex_id_zero_base:
case nir_intrinsic_load_vertex_id:
if (!ctx->vertex_id) {
sam = ir3_META_TEX_PREFETCH(b);
__ssa_dst(sam)->wrmask = MASK(ncomp); /* dst */
- __ssa_src(sam, get_barycentric_pixel(ctx), 0);
+ __ssa_src(sam, get_barycentric(ctx, IJ_PERSP_PIXEL), 0);
sam->prefetch.input_offset =
ir3_nir_coord_offset(tex->src[idx].src.ssa);
/* make sure not to add irrelevant flags like S2EN */
} else if (ctx->so->type == MESA_SHADER_VERTEX) {
struct ir3_instruction *input = NULL;
struct ir3_instruction *components[4];
+ /* input as setup as frac=0 with "ncomp + frac" components,
+ * this avoids getting a sparse writemask
+ */
unsigned mask = (1 << (ncomp + frac)) - 1;
foreach_input (in, ctx->ir) {
* If the new input that aliases a previously processed input
* sets no new bits, then just bail as there is nothing to see
* here.
- *
- * Note that we don't expect to get an input w/ frac!=0, if we
- * did we'd have to adjust ncomp and frac to cover the entire
- * merged input.
*/
if (!(mask & ~input->regs[0]->wrmask))
return;
input->regs[0]->wrmask |= mask;
}
- ir3_split_dest(ctx->block, components, input, frac, ncomp);
+ ir3_split_dest(ctx->block, components, input, 0, ncomp + frac);
- for (int i = 0; i < ncomp; i++) {
- unsigned idx = (n * 4) + i + frac;
+ for (int i = 0; i < ncomp + frac; i++) {
+ unsigned idx = (n * 4) + i;
compile_assert(ctx, idx < ctx->ninputs);
/* With aliased inputs, since we add to the wrmask above, we
ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
}
+ /* note: this can be wrong for sparse vertex inputs, this happens with
+ * vulkan, only a3xx/a4xx use this value for VS, so it shouldn't matter
+ */
if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
so->total_in += ncomp;
}
case FRAG_RESULT_SAMPLE_MASK:
so->writes_smask = true;
break;
+ case FRAG_RESULT_STENCIL:
+ so->writes_stencilref = true;
+ break;
default:
slot += out->data.index; /* For dual-src blend */
if (slot >= FRAG_RESULT_DATA0)
}
/* Setup inputs: */
- nir_foreach_variable (var, &ctx->s->inputs) {
+ nir_foreach_shader_in_variable (var, ctx->s) {
setup_input(ctx, var);
}
}
/* Setup outputs: */
- nir_foreach_variable (var, &ctx->s->outputs) {
+ nir_foreach_shader_out_variable (var, ctx->s) {
setup_output(ctx, var);
}
projects / mesa.git / blobdiff