freedreno/ir3: make input/output iterators declare cursor ptr

[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c

diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c
index 4a55f578c4500bd9860fd0bb751a937ec3b62725..b3e23db243ede0c4b6050481d1ed1dfe950a9536 100644 (file)
--- a/src/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/freedreno/ir3/ir3_compiler_nir.c
@@ -2963,7 +2963,7 @@ setup_input(struct ir3_context *ctx, nir_variable *in)
                        ctx->inputs[idx] = instr;
                }
        } else if (ctx->so->type == MESA_SHADER_VERTEX) {
-               struct ir3_instruction *input = NULL, *in;
+               struct ir3_instruction *input = NULL;
                struct ir3_instruction *components[4];
                unsigned mask = (1 << (ncomp + frac)) - 1;
 
@@ -3362,7 +3362,6 @@ fixup_binning_pass(struct ir3_context *ctx)
                        so->outputs[j] = so->outputs[i];
 
                        /* fixup outidx to point to new output table entry: */
-                       struct ir3_instruction *out;
                        foreach_output (out, ir) {
                                if (out->collect.outidx == i) {
                                        out->collect.outidx = j;
@@ -3426,6 +3425,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
        struct ir3_context *ctx;
        struct ir3 *ir;
        int ret = 0, max_bary;
+       bool progress;
 
        assert(!so->ir);
 
@@ -3554,16 +3554,24 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
 
        ir3_debug_print(ir, "AFTER: nir->ir3");
 
-       IR3_PASS(ir, ir3_cf);
-       IR3_PASS(ir, ir3_cp, so);
+       do {
+               progress = false;
+
+               progress |= IR3_PASS(ir, ir3_cf);
+               progress |= IR3_PASS(ir, ir3_cp, so);
+               progress |= IR3_PASS(ir, ir3_dce, so);
+       } while (progress);
 
        /* at this point, for binning pass, throw away unneeded outputs:
         * Note that for a6xx and later, we do this after ir3_cp to ensure
         * that the uniform/constant layout for BS and VS matches, so that
         * we can re-use same VS_CONST state group.
         */
-       if (so->binning_pass && (ctx->compiler->gpu_id >= 600))
+       if (so->binning_pass && (ctx->compiler->gpu_id >= 600)) {
                fixup_binning_pass(ctx);
+               /* cleanup the result of removing unneeded outputs: */
+               while (IR3_PASS(ir, ir3_dce, so)) {}
+       }
 
        IR3_PASS(ir, ir3_sched_add_deps);
 
@@ -3572,7 +3580,8 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
         */
        IR3_PASS(ir, ir3_group);
 
-       IR3_PASS(ir, ir3_dce, so);
+       /* At this point, all the dead code should be long gone: */
+       assert(!IR3_PASS(ir, ir3_dce, so));
 
        ret = ir3_sched(ir);
        if (ret) {
@@ -3628,7 +3637,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
                ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
        } else if (so->num_sampler_prefetch) {
                assert(so->type == MESA_SHADER_FRAGMENT);
-               struct ir3_instruction *instr, *precolor[2];
+               struct ir3_instruction *precolor[2];
                int idx = 0;
 
                foreach_input (instr, ir) {
@@ -3675,7 +3684,6 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
        for (unsigned i = 0; i < so->outputs_count; i++)
                so->outputs[i].regid = INVALID_REG;
 
-       struct ir3_instruction *out;
        foreach_output (out, ir) {
                assert(out->opc == OPC_META_COLLECT);
                unsigned outidx = out->collect.outidx;
@@ -3684,7 +3692,6 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
                so->outputs[outidx].half  = !!(out->regs[0]->flags & IR3_REG_HALF);
        }
 
-       struct ir3_instruction *in;
        foreach_input (in, ir) {
                assert(in->opc == OPC_META_INPUT);
                unsigned inidx = in->input.inidx;