* src instruction and create a mov. This is easier for cp
* to eliminate.
*
+ * NOTE: a3xx definitely seen not working with flat bary.f. Same test
+ * uses ldlv on a4xx+, so not definitive. Seems rare enough to apply
+ * everywhere.
+ *
* TODO probably opc_cat==4 is ok too
*/
if (alu->src[0].src.is_ssa &&
+ src[0]->opc != OPC_BARY_F &&
(list_length(&alu->src[0].src.ssa->uses) == 1) &&
((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
src[0]->flags |= IR3_INSTR_SAT;
ctx->inputs[idx] = instr;
}
} else if (ctx->so->type == MESA_SHADER_VERTEX) {
- struct ir3_instruction *input = NULL, *in;
+ struct ir3_instruction *input = NULL;
struct ir3_instruction *components[4];
unsigned mask = (1 << (ncomp + frac)) - 1;
so->writes_smask = true;
break;
default:
+ slot += out->data.index; /* For dual-src blend */
if (slot >= FRAG_RESULT_DATA0)
break;
ir3_context_error(ctx, "unknown FS output name: %s\n",
so->outputs[j] = so->outputs[i];
/* fixup outidx to point to new output table entry: */
- struct ir3_instruction *out;
foreach_output (out, ir) {
if (out->collect.outidx == i) {
out->collect.outidx = j;
struct ir3_context *ctx;
struct ir3 *ir;
int ret = 0, max_bary;
+ bool progress;
assert(!so->ir);
}
}
- /* at this point, for binning pass, throw away unneeded outputs: */
- if (so->binning_pass && (ctx->compiler->gpu_id < 600))
- fixup_binning_pass(ctx);
-
- ir3_debug_print(ir, "BEFORE CF");
-
- ir3_cf(ir);
-
- ir3_debug_print(ir, "BEFORE CP");
-
- ir3_cp(ir, so);
-
- /* at this point, for binning pass, throw away unneeded outputs:
- * Note that for a6xx and later, we do this after ir3_cp to ensure
- * that the uniform/constant layout for BS and VS matches, so that
- * we can re-use same VS_CONST state group.
- */
- if (so->binning_pass && (ctx->compiler->gpu_id >= 600))
- fixup_binning_pass(ctx);
-
/* for a6xx+, binning and draw pass VS use same VBO state, so we
* need to make sure not to remove any inputs that are used by
* the nonbinning VS.
}
}
- ir3_debug_print(ir, "BEFORE GROUPING");
+ /* at this point, for binning pass, throw away unneeded outputs: */
+ if (so->binning_pass && (ctx->compiler->gpu_id < 600))
+ fixup_binning_pass(ctx);
- ir3_sched_add_deps(ir);
+ ir3_debug_print(ir, "AFTER: nir->ir3");
- /* Group left/right neighbors, inserting mov's where needed to
- * solve conflicts:
- */
- ir3_group(ir);
+ do {
+ progress = false;
- ir3_debug_print(ir, "AFTER GROUPING");
+ progress |= IR3_PASS(ir, ir3_cf);
+ progress |= IR3_PASS(ir, ir3_cp, so);
+ progress |= IR3_PASS(ir, ir3_dce, so);
+ } while (progress);
+
+ /* at this point, for binning pass, throw away unneeded outputs:
+ * Note that for a6xx and later, we do this after ir3_cp to ensure
+ * that the uniform/constant layout for BS and VS matches, so that
+ * we can re-use same VS_CONST state group.
+ */
+ if (so->binning_pass && (ctx->compiler->gpu_id >= 600)) {
+ fixup_binning_pass(ctx);
+ /* cleanup the result of removing unneeded outputs: */
+ while (IR3_PASS(ir, ir3_dce, so)) {}
+ }
- ir3_dce(ir, so);
+ IR3_PASS(ir, ir3_sched_add_deps);
- ir3_debug_print(ir, "AFTER DCE");
+ /* Group left/right neighbors, inserting mov's where needed to
+ * solve conflicts:
+ */
+ IR3_PASS(ir, ir3_group);
- /* do Sethi–Ullman numbering before scheduling: */
- ir3_sun(ir);
+ /* At this point, all the dead code should be long gone: */
+ assert(!IR3_PASS(ir, ir3_dce, so));
ret = ir3_sched(ir);
if (ret) {
goto out;
}
- ir3_debug_print(ir, "AFTER SCHED");
+ ir3_debug_print(ir, "AFTER: ir3_sched");
/* Pre-assign VS inputs on a6xx+ binning pass shader, to align
* with draw pass VS, so binning and draw pass can both use the
ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
} else if (so->num_sampler_prefetch) {
assert(so->type == MESA_SHADER_FRAGMENT);
- struct ir3_instruction *instr, *precolor[2];
+ struct ir3_instruction *precolor[2];
int idx = 0;
foreach_input (instr, ir) {
goto out;
}
- ir3_postsched(ctx);
- ir3_debug_print(ir, "AFTER POSTSCHED");
+ IR3_PASS(ir, ir3_postsched);
if (compiler->gpu_id >= 600) {
- if (ir3_a6xx_fixup_atomic_dests(ir, so)) {
- ir3_debug_print(ir, "AFTER ATOMIC FIXUP");
- }
+ IR3_PASS(ir, ir3_a6xx_fixup_atomic_dests, so);
}
if (so->type == MESA_SHADER_FRAGMENT)
for (unsigned i = 0; i < so->outputs_count; i++)
so->outputs[i].regid = INVALID_REG;
- struct ir3_instruction *out;
foreach_output (out, ir) {
assert(out->opc == OPC_META_COLLECT);
unsigned outidx = out->collect.outidx;
so->outputs[outidx].half = !!(out->regs[0]->flags & IR3_REG_HALF);
}
- struct ir3_instruction *in;
foreach_input (in, ir) {
assert(in->opc == OPC_META_INPUT);
unsigned inidx = in->input.inidx;
/* We need to do legalize after (for frag shader's) the "bary.f"
* offsets (inloc) have been assigned.
*/
- ir3_legalize(ir, so, &max_bary);
-
- ir3_debug_print(ir, "AFTER LEGALIZE");
+ IR3_PASS(ir, ir3_legalize, so, &max_bary);
/* Set (ss)(sy) on first TCS and GEOMETRY instructions, since we don't
* know what we might have to wait on when coming in from VS chsh.
if (so->type == MESA_SHADER_FRAGMENT)
so->total_in = max_bary + 1;
- so->max_sun = ir->max_sun;
-
/* Collect sampling instructions eligible for pre-dispatch. */
collect_tex_prefetches(ctx, ir);