nir: Rename nir_intrinsic_barrier to control_barrier

[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c

diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c
index bc4cdae0e93b9ff2b240921cf89c56f03fe84611..f1ba10456ed78ad6592c982c9f898bdca6cba3ea 100644 (file)
--- a/src/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/freedreno/ir3/ir3_compiler_nir.c
@@ -1155,7 +1155,7 @@ emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
        struct ir3_instruction *barrier;
 
        switch (intr->intrinsic) {
-       case nir_intrinsic_barrier:
+       case nir_intrinsic_control_barrier:
                barrier = ir3_BAR(b);
                barrier->cat7.g = true;
                barrier->cat7.l = true;
@@ -1536,7 +1536,7 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
                                         * that is easier than mapping things back to a
                                         * nir_variable to figure out what it is.
                                         */
-                                       dst[i] = ctx->ir->inputs[inloc];
+                                       dst[i] = ctx->inputs[inloc];
                                }
                        }
                } else {
@@ -1641,7 +1641,7 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
                        ctx->so->no_earlyz = true;
                dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
                break;
-       case nir_intrinsic_barrier:
+       case nir_intrinsic_control_barrier:
        case nir_intrinsic_memory_barrier:
        case nir_intrinsic_group_memory_barrier:
        case nir_intrinsic_memory_barrier_atomic_counter:
@@ -1671,6 +1671,12 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
                }
                dst[0] = ctx->basevertex;
                break;
+       case nir_intrinsic_load_base_instance:
+               if (!ctx->base_instance) {
+                       ctx->base_instance = create_driver_param(ctx, IR3_DP_INSTID_BASE);
+               }
+               dst[0] = ctx->base_instance;
+               break;
        case nir_intrinsic_load_vertex_id_zero_base:
        case nir_intrinsic_load_vertex_id:
                if (!ctx->vertex_id) {
@@ -2878,6 +2884,10 @@ pack_inlocs(struct ir3_context *ctx)
                                unsigned j = inloc % 4;
 
                                instr->regs[1]->iim_val = so->inputs[i].inloc + j;
+                       } else if (instr->opc == OPC_META_TEX_PREFETCH) {
+                               unsigned i = instr->prefetch.input_offset / 4;
+                               unsigned j = instr->prefetch.input_offset % 4;
+                               instr->prefetch.input_offset = so->inputs[i].inloc + j;
                        }
                }
        }
@@ -3491,7 +3501,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
                assert(in->opc == OPC_META_INPUT);
                unsigned inidx = in->input.inidx;
 
-               if (pre_assign_inputs) {
+               if (pre_assign_inputs && !so->inputs[inidx].sysval) {
                        if (VALIDREG(so->nonbinning->inputs[inidx].regid)) {
                                compile_assert(ctx, in->regs[0]->num ==
                                                so->nonbinning->inputs[inidx].regid);