freedreno/ir3: make compile fails more visible

[mesa.git] / src / freedreno / ir3 / ir3_context.c

diff --git a/src/freedreno/ir3/ir3_context.c b/src/freedreno/ir3/ir3_context.c
index 527cd73a66449089f7ca1adefa585ce257a52468..522c6f69aca976abd4f329d95bf6fd8d3d775f4f 100644 (file)
--- a/src/freedreno/ir3/ir3_context.c
+++ b/src/freedreno/ir3/ir3_context.c
@@ -74,8 +74,7 @@ ir3_context_init(struct ir3_compiler *compiler,
         */
 
        ctx->s = nir_shader_clone(ctx, so->shader->nir);
-       if (ir3_key_lowers_nir(&so->key))
-               ir3_optimize_nir(so->shader, ctx->s, &so->key);
+       ir3_nir_lower_variant(so, ctx->s);
 
        /* this needs to be the last pass run, so do this here instead of
         * in ir3_optimize_nir():
@@ -256,9 +255,11 @@ ir3_put_dst(struct ir3_context *ctx, nir_dest *dst)
        if (bit_size == 16) {
                for (unsigned i = 0; i < ctx->last_dst_n; i++) {
                        struct ir3_instruction *dst = ctx->last_dst[i];
-                       dst->regs[0]->flags |= IR3_REG_HALF;
+                       ir3_set_dst_type(dst, true);
+                       ir3_fixup_src_type(dst);
                        if (dst->opc == OPC_META_SPLIT) {
-                               dst->regs[1]->instr->regs[0]->flags |= IR3_REG_HALF;
+                               ir3_set_dst_type(ssa(dst->regs[1]), true);
+                               ir3_fixup_src_type(ssa(dst->regs[1]));
                                dst->regs[1]->flags |= IR3_REG_HALF;
                        }
                }
@@ -423,11 +424,7 @@ create_addr0(struct ir3_block *block, struct ir3_instruction *src, int align)
 {
        struct ir3_instruction *instr, *immed;
 
-       /* TODO in at least some cases, the backend could probably be
-        * made clever enough to propagate IR3_REG_HALF..
-        */
        instr = ir3_COV(block, src, TYPE_U32, TYPE_S16);
-       instr->regs[0]->flags |= IR3_REG_HALF;
 
        switch(align){
        case 1:
@@ -435,41 +432,29 @@ create_addr0(struct ir3_block *block, struct ir3_instruction *src, int align)
                break;
        case 2:
                /* src *= 2     => src <<= 1: */
-               immed = create_immed(block, 1);
-               immed->regs[0]->flags |= IR3_REG_HALF;
-
+               immed = create_immed_typed(block, 1, TYPE_S16);
                instr = ir3_SHL_B(block, instr, 0, immed, 0);
-               instr->regs[0]->flags |= IR3_REG_HALF;
-               instr->regs[1]->flags |= IR3_REG_HALF;
                break;
        case 3:
                /* src *= 3: */
-               immed = create_immed(block, 3);
-               immed->regs[0]->flags |= IR3_REG_HALF;
-
+               immed = create_immed_typed(block, 3, TYPE_S16);
                instr = ir3_MULL_U(block, instr, 0, immed, 0);
-               instr->regs[0]->flags |= IR3_REG_HALF;
-               instr->regs[1]->flags |= IR3_REG_HALF;
                break;
        case 4:
                /* src *= 4 => src <<= 2: */
-               immed = create_immed(block, 2);
-               immed->regs[0]->flags |= IR3_REG_HALF;
-
+               immed = create_immed_typed(block, 2, TYPE_S16);
                instr = ir3_SHL_B(block, instr, 0, immed, 0);
-               instr->regs[0]->flags |= IR3_REG_HALF;
-               instr->regs[1]->flags |= IR3_REG_HALF;
                break;
        default:
                unreachable("bad align");
                return NULL;
        }
 
+       instr->regs[0]->flags |= IR3_REG_HALF;
+
        instr = ir3_MOV(block, instr, TYPE_S16);
        instr->regs[0]->num = regid(REG_A0, 0);
        instr->regs[0]->flags &= ~IR3_REG_SSA;
-       instr->regs[0]->flags |= IR3_REG_HALF;
-       instr->regs[1]->flags |= IR3_REG_HALF;
 
        return instr;
 }
@@ -478,12 +463,10 @@ static struct ir3_instruction *
 create_addr1(struct ir3_block *block, unsigned const_val)
 {
 
-       struct ir3_instruction *immed = create_immed(block, const_val);
+       struct ir3_instruction *immed = create_immed_typed(block, const_val, TYPE_S16);
        struct ir3_instruction *instr = ir3_MOV(block, immed, TYPE_S16);
        instr->regs[0]->num = regid(REG_A0, 1);
        instr->regs[0]->flags &= ~IR3_REG_SSA;
-       instr->regs[0]->flags |= IR3_REG_HALF;
-       instr->regs[1]->flags |= IR3_REG_HALF;
        return instr;
 }