freedreno/ir3: split out regmask

[mesa.git] / src / freedreno / ir3 / ir3_context.h

diff --git a/src/freedreno/ir3/ir3_context.h b/src/freedreno/ir3/ir3_context.h
index c3e16ba37fa9bcbd7b2c7206534983fab463b65d..30caf9d7b852a764d06ef10dfaf224817dc10156 100644 (file)
--- a/src/freedreno/ir3/ir3_context.h
+++ b/src/freedreno/ir3/ir3_context.h
@@ -52,6 +52,18 @@ struct ir3_context {
        struct ir3 *ir;
        struct ir3_shader_variant *so;
 
+       /* Tables of scalar inputs/outputs.  Because of the way varying packing
+        * works, we could have inputs w/ fractional location, which is a bit
+        * awkward to deal with unless we keep track of the split scalar in/
+        * out components.
+        *
+        * These *only* have inputs/outputs that are touched by load_*input and
+        * store_output.
+        */
+       unsigned ninputs, noutputs;
+       struct ir3_instruction **inputs;
+       struct ir3_instruction **outputs;
+
        struct ir3_block *block;      /* the current block */
        struct ir3_block *in_block;   /* block created for shader inputs */
 
@@ -65,17 +77,26 @@ struct ir3_context {
         * inputs.  So we do all the input tracking normally and fix
         * things up after compile_instructions()
         */
-       struct ir3_instruction *ij_pixel, *ij_sample, *ij_centroid, *ij_size;
+       struct ir3_instruction *ij[IJ_COUNT];
 
        /* for fragment shaders, for gl_FrontFacing and gl_FragCoord: */
        struct ir3_instruction *frag_face, *frag_coord;
 
        /* For vertex shaders, keep track of the system values sources */
-       struct ir3_instruction *vertex_id, *basevertex, *instance_id;
+       struct ir3_instruction *vertex_id, *basevertex, *instance_id, *base_instance, *draw_id;
 
        /* For fragment shaders: */
        struct ir3_instruction *samp_id, *samp_mask_in;
 
+       /* For geometry shaders: */
+       struct ir3_instruction *primitive_id;
+       struct ir3_instruction *gs_header;
+
+       /* For tessellation shaders: */
+       struct ir3_instruction *patch_vertices_in;
+       struct ir3_instruction *tcs_header;
+       struct ir3_instruction *tess_coord;
+
        /* Compute shader inputs: */
        struct ir3_instruction *local_invocation_id, *work_group_id;
 
@@ -99,7 +120,14 @@ struct ir3_context {
         * src used for an array of vec1 cannot be also used for an
         * array of vec4.
         */
-       struct hash_table *addr_ht[4];
+       struct hash_table *addr0_ht[4];
+
+       /* The same for a1.x. We only support immediate values for a1.x, as this
+        * is the only use so far.
+        */
+       struct hash_table_u64 *addr1_ht;
+
+       struct hash_table *sel_cond_conversions;
 
        /* last dst array, for indirect we need to insert a var-store.
         */
@@ -118,6 +146,8 @@ struct ir3_context {
 
        unsigned max_texture_index;
 
+       unsigned prefetch_limit;
+
        /* set if we encounter something we can't handle yet, so we
         * can bail cleanly and fallback to TGSI compiler f/e
         */
@@ -129,8 +159,12 @@ struct ir3_context_funcs {
                        struct ir3_instruction **dst);
        void (*emit_intrinsic_store_ssbo)(struct ir3_context *ctx, nir_intrinsic_instr *intr);
        struct ir3_instruction * (*emit_intrinsic_atomic_ssbo)(struct ir3_context *ctx, nir_intrinsic_instr *intr);
+       void (*emit_intrinsic_load_image)(struct ir3_context *ctx, nir_intrinsic_instr *intr,
+                       struct ir3_instruction **dst);
        void (*emit_intrinsic_store_image)(struct ir3_context *ctx, nir_intrinsic_instr *intr);
        struct ir3_instruction * (*emit_intrinsic_atomic_image)(struct ir3_context *ctx, nir_intrinsic_instr *intr);
+       void (*emit_intrinsic_image_size)(struct ir3_context *ctx, nir_intrinsic_instr *intr,
+                       struct ir3_instruction **dst);
 };
 
 extern const struct ir3_context_funcs ir3_a4xx_funcs;
@@ -140,13 +174,6 @@ struct ir3_context * ir3_context_init(struct ir3_compiler *compiler,
                struct ir3_shader_variant *so);
 void ir3_context_free(struct ir3_context *ctx);
 
-/* gpu pointer size in units of 32bit registers/slots */
-static inline
-unsigned ir3_pointer_size(struct ir3_context *ctx)
-{
-       return (ctx->compiler->gpu_id >= 500) ? 2 : 1;
-}
-
 struct ir3_instruction ** ir3_get_dst_ssa(struct ir3_context *ctx, nir_ssa_def *dst, unsigned n);
 struct ir3_instruction ** ir3_get_dst(struct ir3_context *ctx, nir_dest *dst, unsigned n);
 struct ir3_instruction * const * ir3_get_src(struct ir3_context *ctx, nir_src *src);
@@ -155,6 +182,9 @@ struct ir3_instruction * ir3_create_collect(struct ir3_context *ctx,
                struct ir3_instruction *const *arr, unsigned arrsz);
 void ir3_split_dest(struct ir3_block *block, struct ir3_instruction **dst,
                struct ir3_instruction *src, unsigned base, unsigned n);
+void ir3_handle_bindless_cat6(struct ir3_instruction *instr, nir_src rsrc);
+void emit_intrinsic_image_size_tex(struct ir3_context *ctx, nir_intrinsic_instr *intr,
+               struct ir3_instruction **dst);
 
 NORETURN void ir3_context_error(struct ir3_context *ctx, const char *format, ...);
 
@@ -162,8 +192,10 @@ NORETURN void ir3_context_error(struct ir3_context *ctx, const char *format, ...
                if (!(cond)) ir3_context_error((ctx), "failed assert: "#cond"\n"); \
        } while (0)
 
-struct ir3_instruction * ir3_get_addr(struct ir3_context *ctx,
+struct ir3_instruction * ir3_get_addr0(struct ir3_context *ctx,
                struct ir3_instruction *src, int align);
+struct ir3_instruction * ir3_get_addr1(struct ir3_context *ctx,
+               unsigned const_val);
 struct ir3_instruction * ir3_get_predicate(struct ir3_context *ctx,
                struct ir3_instruction *src);