tu: Set up glsl types.

[mesa.git] / src / freedreno / ir3 / ir3_nir.c

diff --git a/src/freedreno/ir3/ir3_nir.c b/src/freedreno/ir3/ir3_nir.c
index c692274d8e31a9fdabc4bd2e4b5102ef9f088ec3..50a961f2bad56d108f16a94473cf9769b030d0e8 100644 (file)
--- a/src/freedreno/ir3/ir3_nir.c
+++ b/src/freedreno/ir3/ir3_nir.c
@@ -40,8 +40,7 @@ static const nir_shader_compiler_options options = {
                .lower_flrp32 = true,
                .lower_flrp64 = true,
                .lower_ffract = true,
-               .lower_fmod32 = true,
-               .lower_fmod64 = true,
+               .lower_fmod = true,
                .lower_fdiv = true,
                .lower_isign = true,
                .lower_ldexp = true,
@@ -55,8 +54,8 @@ static const nir_shader_compiler_options options = {
                .lower_helper_invocation = true,
                .lower_bitfield_insert_to_shifts = true,
                .lower_bitfield_extract_to_shifts = true,
-               .lower_bfm = true,
                .use_interpolated_input_intrinsics = true,
+               .lower_rotate = true,
 };
 
 /* we don't want to lower vertex_id to _zero_based on newer gpus: */
@@ -66,8 +65,7 @@ static const nir_shader_compiler_options options_a6xx = {
                .lower_flrp32 = true,
                .lower_flrp64 = true,
                .lower_ffract = true,
-               .lower_fmod32 = true,
-               .lower_fmod64 = true,
+               .lower_fmod = true,
                .lower_fdiv = true,
                .lower_isign = true,
                .lower_ldexp = true,
@@ -81,8 +79,8 @@ static const nir_shader_compiler_options options_a6xx = {
                .lower_helper_invocation = true,
                .lower_bitfield_insert_to_shifts = true,
                .lower_bitfield_extract_to_shifts = true,
-               .lower_bfm = true,
                .use_interpolated_input_intrinsics = true,
+               .lower_rotate = true,
 };
 
 const nir_shader_compiler_options *
@@ -126,7 +124,7 @@ ir3_optimize_loop(nir_shader *s)
                OPT_V(s, nir_lower_vars_to_ssa);
                progress |= OPT(s, nir_opt_copy_prop_vars);
                progress |= OPT(s, nir_opt_dead_write_vars);
-               progress |= OPT(s, nir_lower_alu_to_scalar);
+               progress |= OPT(s, nir_lower_alu_to_scalar, NULL, NULL);
                progress |= OPT(s, nir_lower_phis_to_scalar);
 
                progress |= OPT(s, nir_copy_prop);
@@ -176,7 +174,7 @@ ir3_optimize_loop(nir_shader *s)
        } while (progress);
 }
 
-struct nir_shader *
+void
 ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s,
                const struct ir3_shader_key *key)
 {
@@ -266,7 +264,7 @@ ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s,
 
        OPT_V(s, nir_remove_dead_variables, nir_var_function_temp);
 
-       OPT_V(s, nir_move_load_const);
+       OPT_V(s, nir_opt_sink, nir_move_const_undef);
 
        if (ir3_shader_debug & IR3_DBG_DISASM) {
                debug_printf("----------------------\n");
@@ -283,8 +281,6 @@ ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s,
        if (!key) {
                ir3_setup_const_state(shader, s);
        }
-
-       return s;
 }
 
 static void
@@ -315,8 +311,10 @@ ir3_nir_scan_driver_consts(nir_shader *shader,
                                        layout->ssbo_size.count += 1; /* one const per */
                                        break;
                                case nir_intrinsic_image_deref_atomic_add:
-                               case nir_intrinsic_image_deref_atomic_min:
-                               case nir_intrinsic_image_deref_atomic_max:
+                               case nir_intrinsic_image_deref_atomic_imin:
+                               case nir_intrinsic_image_deref_atomic_umin:
+                               case nir_intrinsic_image_deref_atomic_imax:
+                               case nir_intrinsic_image_deref_atomic_umax:
                                case nir_intrinsic_image_deref_atomic_and:
                                case nir_intrinsic_image_deref_atomic_or:
                                case nir_intrinsic_image_deref_atomic_xor:
@@ -332,6 +330,31 @@ ir3_nir_scan_driver_consts(nir_shader *shader,
                                                layout->image_dims.count;
                                        layout->image_dims.count += 3; /* three const per */
                                        break;
+                               case nir_intrinsic_load_ubo:
+                                       if (nir_src_is_const(intr->src[0])) {
+                                               layout->num_ubos = MAX2(layout->num_ubos,
+                                                               nir_src_as_uint(intr->src[0]) + 1);
+                                       } else {
+                                               layout->num_ubos = shader->info.num_ubos;
+                                       }
+                                       break;
+                               case nir_intrinsic_load_base_vertex:
+                               case nir_intrinsic_load_first_vertex:
+                                       layout->num_driver_params =
+                                               MAX2(layout->num_driver_params, IR3_DP_VTXID_BASE + 1);
+                                       break;
+                               case nir_intrinsic_load_user_clip_plane:
+                                       layout->num_driver_params =
+                                               MAX2(layout->num_driver_params, IR3_DP_UCP7_W + 1);
+                                       break;
+                               case nir_intrinsic_load_num_work_groups:
+                                       layout->num_driver_params =
+                                               MAX2(layout->num_driver_params, IR3_DP_NUM_WORK_GROUPS_Z + 1);
+                                       break;
+                               case nir_intrinsic_load_local_group_size:
+                                       layout->num_driver_params =
+                                               MAX2(layout->num_driver_params, IR3_DP_LOCAL_GROUP_SIZE_Z + 1);
+                                       break;
                                default:
                                        break;
                                }
@@ -350,11 +373,17 @@ ir3_setup_const_state(struct ir3_shader *shader, nir_shader *nir)
 
        ir3_nir_scan_driver_consts(nir, const_state);
 
-       const_state->num_uniforms = nir->num_uniforms;
-       const_state->num_ubos = nir->info.num_ubos;
+       if ((compiler->gpu_id < 500) &&
+                       (shader->stream_output.num_outputs > 0)) {
+               const_state->num_driver_params =
+                       MAX2(const_state->num_driver_params, IR3_DP_VTXCNT_MAX + 1);
+       }
+
+       /* num_driver_params is scalar, align to vec4: */
+       const_state->num_driver_params = align(const_state->num_driver_params, 4);
 
        debug_assert((shader->ubo_state.size % 16) == 0);
-       unsigned constoff = align(shader->ubo_state.size / 16, 4);
+       unsigned constoff = align(shader->ubo_state.size / 16, 8);
        unsigned ptrsz = ir3_pointer_size(compiler);
 
        if (const_state->num_ubos > 0) {
@@ -374,15 +403,9 @@ ir3_setup_const_state(struct ir3_shader *shader, nir_shader *nir)
                constoff += align(cnt, 4) / 4;
        }
 
-       unsigned num_driver_params = 0;
-       if (shader->type == MESA_SHADER_VERTEX) {
-               num_driver_params = IR3_DP_VS_COUNT;
-       } else if (shader->type == MESA_SHADER_COMPUTE) {
-               num_driver_params = IR3_DP_CS_COUNT;
-       }
-
-       const_state->offsets.driver_param = constoff;
-       constoff += align(num_driver_params, 4) / 4;
+       if (const_state->num_driver_params > 0)
+               const_state->offsets.driver_param = constoff;
+       constoff += const_state->num_driver_params / 4;
 
        if ((shader->type == MESA_SHADER_VERTEX) &&
                        (compiler->gpu_id < 500) &&