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[mesa.git] / src / freedreno / ir3 / ir3_nir.c

diff --git a/src/freedreno/ir3/ir3_nir.c b/src/freedreno/ir3/ir3_nir.c
index 61ebc615155af3e3312034b4f6bb0a96f6b75192..d75df2feef4a2ec09f3f26570711c5a8ecfecabd 100644 (file)
--- a/src/freedreno/ir3/ir3_nir.c
+++ b/src/freedreno/ir3/ir3_nir.c
@@ -49,11 +49,12 @@ static const nir_shader_compiler_options options = {
                .vertex_id_zero_based = true,
                .lower_extract_byte = true,
                .lower_extract_word = true,
-               .lower_all_io_to_temps = true,
+               .lower_all_io_to_elements = true,
                .lower_helper_invocation = true,
                .lower_bitfield_insert_to_shifts = true,
                .lower_bitfield_extract_to_shifts = true,
                .lower_bfm = true,
+               .use_interpolated_input_intrinsics = true,
 };
 
 /* we don't want to lower vertex_id to _zero_based on newer gpus: */
@@ -75,11 +76,12 @@ static const nir_shader_compiler_options options_a6xx = {
                .vertex_id_zero_based = false,
                .lower_extract_byte = true,
                .lower_extract_word = true,
-               .lower_all_io_to_temps = true,
+               .lower_all_io_to_elements = true,
                .lower_helper_invocation = true,
                .lower_bitfield_insert_to_shifts = true,
                .lower_bitfield_extract_to_shifts = true,
                .lower_bfm = true,
+               .use_interpolated_input_intrinsics = true,
 };
 
 const nir_shader_compiler_options *
@@ -145,7 +147,7 @@ ir3_optimize_loop(nir_shader *s)
                        OPT(s, nir_copy_prop);
                        OPT(s, nir_opt_dce);
                }
-               progress |= OPT(s, nir_opt_if);
+               progress |= OPT(s, nir_opt_if, false);
                progress |= OPT(s, nir_opt_remove_phis);
                progress |= OPT(s, nir_opt_undef);
 
@@ -193,7 +195,6 @@ ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s,
                debug_printf("----------------------\n");
        }
 
-       OPT_V(s, nir_opt_global_to_local);
        OPT_V(s, nir_lower_regs_to_ssa);
        OPT_V(s, ir3_nir_lower_io_offsets);