printf(".s");
if (instr->flags & IR3_INSTR_A1EN)
printf(".a1en");
+ if (instr->opc == OPC_LDC)
+ printf(".offset%d", instr->cat6.d);
if (instr->flags & IR3_INSTR_B) {
printf(".base%d",
is_tex(instr) ? instr->cat5.tex_base : instr->cat6.base);
}
if (instr->flags & IR3_INSTR_S2EN)
printf(".s2en");
+
+ static const char *cond[0x7] = {
+ "lt",
+ "le",
+ "gt",
+ "ge",
+ "eq",
+ "ne",
+ };
+
+ switch (instr->opc) {
+ case OPC_CMPS_F:
+ case OPC_CMPS_U:
+ case OPC_CMPS_S:
+ case OPC_CMPV_F:
+ case OPC_CMPV_U:
+ case OPC_CMPV_S:
+ printf(".%s", cond[instr->cat2.condition & 0x7]);
+ break;
+ default:
+ break;
+ }
}
}
else if (reg->flags & (IR3_REG_FABS | IR3_REG_SABS))
printf("(abs)");
+ if (reg->flags & IR3_REG_R)
+ printf("(r)");
+
if (reg->flags & IR3_REG_HIGH)
printf("H");
if (reg->flags & IR3_REG_HALF)
if (is_flow(instr) && instr->cat0.target) {
/* the predicate register src is implied: */
- if (instr->opc == OPC_BR) {
- printf(" %sp0.x", instr->cat0.inv ? "!" : "");
+ if (instr->opc == OPC_B) {
+ printf("r %sp0.x", instr->cat0.inv ? "!" : "");
}
printf(", target=block%u", block_id(instr->cat0.target));
}
unsigned i = 0;
tab(lvl+1);
printf("pred: ");
- set_foreach(block->predecessors, entry) {
+ set_foreach (block->predecessors, entry) {
struct ir3_block *pred = (struct ir3_block *)entry->key;
if (i++)
printf(", ");
foreach_block (block, &ir->block_list)
print_block(block, 0);
- struct ir3_instruction *out;
foreach_output_n (out, i, ir) {
printf("out%d: ", i);
print_instr(out, 0);