freedreno/ir3/sched: avoid scheduling outputs

[mesa.git] / src / freedreno / ir3 / ir3_ra.h

diff --git a/src/freedreno/ir3/ir3_ra.h b/src/freedreno/ir3/ir3_ra.h
index 4c5cab0edfc3a29c0c6e2658a7fc3972838190a1..7acfdd0443d88dc05d35ef72b1ebd9268ab0a2d4 100644 (file)
--- a/src/freedreno/ir3/ir3_ra.h
+++ b/src/freedreno/ir3/ir3_ra.h
@@ -27,14 +27,8 @@
 #ifndef IR3_RA_H_
 #define IR3_RA_H_
 
-//#include "util/u_math.h"
-//#include "util/register_allocate.h"
-//#include "util/ralloc.h"
 #include "util/bitset.h"
 
-//#include "ir3.h"
-//#include "ir3_compiler.h"
-
 
 static const unsigned class_sizes[] = {
        1, 2, 3, 4,
@@ -63,9 +57,27 @@ static const unsigned high_class_sizes[] = {
 #define NUM_HIGH_REGS        (4 * 8)   /* r48 to r55 */
 #define FIRST_HIGH_REG       (4 * 48)
 /* Number of virtual regs in a given class: */
-#define CLASS_REGS(i)        (NUM_REGS - (class_sizes[i] - 1))
-#define HALF_CLASS_REGS(i)   (NUM_REGS - (half_class_sizes[i] - 1))
-#define HIGH_CLASS_REGS(i)   (NUM_HIGH_REGS - (high_class_sizes[i] - 1))
+
+static inline unsigned CLASS_REGS(unsigned i)
+{
+       assert(i < class_count);
+
+       return (NUM_REGS - (class_sizes[i] - 1));
+}
+
+static inline unsigned HALF_CLASS_REGS(unsigned i)
+{
+       assert(i < half_class_count);
+
+       return (NUM_REGS - (half_class_sizes[i] - 1));
+}
+
+static inline unsigned HIGH_CLASS_REGS(unsigned i)
+{
+       assert(i < high_class_count);
+
+       return (NUM_HIGH_REGS - (high_class_sizes[i] - 1));
+}
 
 #define HALF_OFFSET          (class_count)
 #define HIGH_OFFSET          (class_count + half_class_count)
@@ -76,6 +88,26 @@ struct ir3_ra_reg_set {
        unsigned int classes[class_count];
        unsigned int half_classes[half_class_count];
        unsigned int high_classes[high_class_count];
+
+       /* The virtual register space flattens out all the classes,
+        * starting with full, followed by half and then high, ie:
+        *
+        *   scalar full  (starting at zero)
+        *   vec2 full
+        *   vec3 full
+        *   ...
+        *   vecN full
+        *   scalar half  (starting at first_half_reg)
+        *   vec2 half
+        *   ...
+        *   vecN half
+        *   scalar high  (starting at first_high_reg)
+        *   ...
+        *   vecN high
+        *
+        */
+       unsigned first_half_reg, first_high_reg;
+
        /* maps flat virtual register space to base gpr: */
        uint16_t *ra_reg_to_gpr;
        /* maps cls,gpr to flat virtual register space: */
@@ -112,6 +144,8 @@ struct ir3_ra_ctx {
        bool scalar_pass;
 
        unsigned alloc_count;
+       unsigned r0_xyz_nodes; /* ra node numbers for r0.[xyz] precolors */
+       unsigned hr0_xyz_nodes; /* ra node numbers for hr0.[xyz] precolors pre-a6xx */
        /* one per class, plus one slot for arrays: */
        unsigned class_alloc_count[total_class_count + 1];
        unsigned class_base[total_class_count + 1];
@@ -171,20 +205,6 @@ scalar_name(struct ir3_ra_ctx *ctx, struct ir3_instruction *instr, unsigned n)
        return ra_name(ctx, &ctx->instrd[instr->ip]) + n;
 }
 
-static inline bool
-writes_gpr(struct ir3_instruction *instr)
-{
-       if (dest_regs(instr) == 0)
-               return false;
-       /* is dest a normal temp register: */
-       struct ir3_register *reg = instr->regs[0];
-       debug_assert(!(reg->flags & (IR3_REG_CONST | IR3_REG_IMMED)));
-       if ((reg->num == regid(REG_A0, 0)) ||
-                       (reg->num == regid(REG_P0, 0)))
-               return false;
-       return true;
-}
-
 #define NO_NAME ~0
 
 /*
@@ -333,5 +353,6 @@ __ra_init_use_itr(struct ir3_ra_ctx *ctx, struct ir3_instruction *instr)
             __name != NO_NAME; __name = __ra_itr_pop(__ctx))
 
 int ra_size_to_class(unsigned sz, bool half, bool high);
+int ra_class_to_size(unsigned class, bool *half, bool *high);
 
 #endif  /* IR3_RA_H_ */