ir3: Add ir3_trim_constlen()

[mesa.git] / src / freedreno / ir3 / ir3_ra.h

diff --git a/src/freedreno/ir3/ir3_ra.h b/src/freedreno/ir3/ir3_ra.h
index 437223bd1de11e6c0252b61935d1b302742f3cd1..aa703ae645f9b6bdbfa68f7887751dc8c3f43162 100644 (file)
--- a/src/freedreno/ir3/ir3_ra.h
+++ b/src/freedreno/ir3/ir3_ra.h
@@ -89,6 +89,14 @@ struct ir3_ra_reg_set {
        unsigned int half_classes[half_class_count];
        unsigned int high_classes[high_class_count];
 
+       /* pre-fetched tex dst is limited, on current gens to regs
+        * 0x3f and below.  An additional register class, with one
+        * vreg, that is setup to conflict with any regs above that
+        * limit.
+        */
+       unsigned prefetch_exclude_class;
+       unsigned prefetch_exclude_reg;
+
        /* The virtual register space flattens out all the classes,
         * starting with full, followed by half and then high, ie:
         *
@@ -145,7 +153,8 @@ struct ir3_ra_ctx {
 
        unsigned alloc_count;
        unsigned r0_xyz_nodes; /* ra node numbers for r0.[xyz] precolors */
-       unsigned hr0_xyz_nodes; /* ra node numbers for hr0.[xyz] precolors pre-a6xx */
+       unsigned hr0_xyz_nodes; /* ra node numbers for hr0.[xyz] precolors */
+       unsigned prefetch_exclude_node;
        /* one per class, plus one slot for arrays: */
        unsigned class_alloc_count[total_class_count + 1];
        unsigned class_base[total_class_count + 1];