freedreno/ir3: build binning variant at same time as draw variant

[mesa.git] / src / freedreno / ir3 / ir3_ra_regset.c

diff --git a/src/freedreno/ir3/ir3_ra_regset.c b/src/freedreno/ir3/ir3_ra_regset.c
index 48fd9f106e8d45727ab971470b55a7e442a3211f..c9e6c8e21cbb52c1f98097723414ee460aedf727 100644 (file)
--- a/src/freedreno/ir3/ir3_ra_regset.c
+++ b/src/freedreno/ir3/ir3_ra_regset.c
@@ -105,7 +105,7 @@ setup_conflicts(struct ir3_ra_reg_set *set)
  * really just four scalar registers.  Don't let that confuse you.)
  */
 struct ir3_ra_reg_set *
-ir3_ra_alloc_reg_set(struct ir3_compiler *compiler)
+ir3_ra_alloc_reg_set(struct ir3_compiler *compiler, bool mergedregs)
 {
        struct ir3_ra_reg_set *set = rzalloc(compiler, struct ir3_ra_reg_set);
        unsigned ra_reg_count, reg, base;
@@ -195,7 +195,7 @@ ir3_ra_alloc_reg_set(struct ir3_compiler *compiler)
         * And finally setup conflicts.  Starting a6xx, half precision regs
         * conflict w/ full precision regs (when using MERGEDREGS):
         */
-       if (compiler->gpu_id >= 600) {
+       if (mergedregs) {
                for (unsigned i = 0; i < CLASS_REGS(0) / 2; i++) {
                        unsigned freg  = set->gpr_to_ra_reg[0][i];
                        unsigned hreg0 = set->gpr_to_ra_reg[0 + HALF_OFFSET][(i * 2) + 0];