{
struct ir3_instruction *src;
- foreach_ssa_src_n(src, n, instr) {
+ foreach_ssa_src_n (src, n, instr) {
if (__is_false_dep(instr, n))
continue;
if (instr->block != src->block)
debug_assert(is_scheduled(orig_instr));
- foreach_ssa_src_n(src, n, new_instr) {
+ foreach_ssa_src_n (src, n, new_instr) {
if (__is_false_dep(new_instr, n))
continue;
if (is_half(new_instr)) {
{
struct ir3_instruction *src;
- foreach_ssa_src_n(src, n, instr) {
+ foreach_ssa_src_n (src, n, instr) {
if (__is_false_dep(instr, n))
continue;
use_instr(src);
/* Shader outputs are also used:
*/
struct ir3_instruction *out;
- foreach_output(out, ir)
+ foreach_output (out, ir)
use_instr(out);
}
could_sched(struct ir3_instruction *instr, struct ir3_instruction *src)
{
struct ir3_instruction *other_src;
- foreach_ssa_src(other_src, instr) {
+ foreach_ssa_src (other_src, instr) {
/* if dependency not scheduled, we aren't ready yet: */
if ((src != other_src) && !is_scheduled(other_src)) {
return false;
}
/* find unscheduled srcs: */
- foreach_ssa_src(src, instr) {
+ foreach_ssa_src (src, instr) {
if (!is_scheduled(src) && (src->block == instr->block)) {
debug_assert(nsrcs < ARRAY_SIZE(srcs));
srcs[nsrcs++] = src;
int new_live = dest_regs(instr);
int old_live = 0;
- foreach_ssa_src_n(src, n, instr) {
+ foreach_ssa_src_n (src, n, instr) {
if (__is_false_dep(instr, n))
continue;
struct ir3_instruction *src2;
bool last_use = true;
- foreach_ssa_src(src2, src) {
+ foreach_ssa_src (src2, src) {
if (src2->use_count > 1) {
last_use = false;
break;