ir3, freedreno: Round up constlen earlier

[mesa.git] / src / freedreno / ir3 / ir3_shader.h

diff --git a/src/freedreno/ir3/ir3_shader.h b/src/freedreno/ir3/ir3_shader.h
index 0123af6763561f7f3c072228d92573ff073034e8..2529de73509685dde277b3493f16c4ea9e0a9bed 100644 (file)
--- a/src/freedreno/ir3/ir3_shader.h
+++ b/src/freedreno/ir3/ir3_shader.h
@@ -55,9 +55,10 @@ enum ir3_driver_param {
        IR3_DP_CS_COUNT   = 8,   /* must be aligned to vec4 */
 
        /* vertex shader driver params: */
-       IR3_DP_VTXID_BASE = 0,
-       IR3_DP_VTXCNT_MAX = 1,
+       IR3_DP_DRAWID = 0,
+       IR3_DP_VTXID_BASE = 1,
        IR3_DP_INSTID_BASE = 2,
+       IR3_DP_VTXCNT_MAX = 3,
        /* user-clip-plane components, up to 8x vec4's: */
        IR3_DP_UCP0_X     = 4,
        /* .... */
@@ -72,20 +73,31 @@ enum ir3_driver_param {
 #define IR3_MAX_SO_OUTPUTS       64
 #define IR3_MAX_UBO_PUSH_RANGES  32
 
+/**
+ * Description of a lowered UBO.
+ */
+struct ir3_ubo_info {
+       uint32_t block; /* Which constant block */
+       uint16_t bindless_base; /* For bindless, which base register is used */
+       bool bindless;
+};
 
+/**
+ * Description of a range of a lowered UBO access.
+ *
+ * Drivers should not assume that there are not multiple disjoint
+ * lowered ranges of a single UBO.
+ */
 struct ir3_ubo_range {
+       struct ir3_ubo_info ubo;
        uint32_t offset; /* start offset to push in the const register file */
-       uint32_t block; /* Which constant block */
        uint32_t start, end; /* range of block that's actually used */
-       uint16_t bindless_base; /* For bindless, which base register is used */
-       bool bindless;
 };
 
 struct ir3_ubo_analysis_state {
        struct ir3_ubo_range range[IR3_MAX_UBO_PUSH_RANGES];
        uint32_t num_enabled;
        uint32_t size;
-       uint32_t lower_count;
        uint32_t cmdstream_size; /* for per-gen backend to stash required cmdstream size */
 };
 
@@ -130,7 +142,6 @@ struct ir3_ubo_analysis_state {
  */
 struct ir3_const_state {
        unsigned num_ubos;
-       unsigned num_reserved_user_consts;
        unsigned num_driver_params;   /* scalar */
 
        struct {
@@ -469,6 +480,8 @@ struct ir3_shader_variant {
         */
        unsigned constlen;
 
+       struct ir3_const_state *const_state;
+
        /* About Linkage:
         *   + Let the frag shader determine the position/compmask for the
         *     varyings, since it is the place where we know if the varying
@@ -496,6 +509,12 @@ struct ir3_shader_variant {
        } outputs[32 + 2];  /* +POSITION +PSIZE */
        bool writes_pos, writes_smask, writes_psize;
 
+       /* Size in dwords of all outputs for VS, size of entire patch for HS. */
+       uint32_t output_size;
+
+       /* Map from driver_location to byte offset in per-primitive storage */
+       unsigned output_loc[32];
+
        /* attributes (VS) / varyings (FS):
         * Note that sysval's should come *after* normal inputs.
         */
@@ -622,7 +641,7 @@ struct ir3_shader {
 
        struct ir3_compiler *compiler;
 
-       struct ir3_const_state const_state;
+       unsigned num_reserved_user_consts;
 
        struct nir_shader *nir;
        struct ir3_stream_output_info stream_output;
@@ -630,21 +649,23 @@ struct ir3_shader {
        struct ir3_shader_variant *variants;
        mtx_t variants_lock;
 
-       uint32_t output_size; /* Size in dwords of all outputs for VS, size of entire patch for HS. */
-
-       /* Map from driver_location to byte offset in per-primitive storage */
-       unsigned output_loc[32];
-
        /* Bitmask of bits of the shader key used by this shader.  Used to avoid
         * recompiles for GL NOS that doesn't actually apply to the shader.
         */
        struct ir3_shader_key key_mask;
 };
 
+/**
+ * In order to use the same cmdstream, in particular constlen setup and const
+ * emit, for both binning and draw pass (a6xx+), the binning pass re-uses it's
+ * corresponding draw pass shaders const_state.
+ */
 static inline struct ir3_const_state *
 ir3_const_state(const struct ir3_shader_variant *v)
 {
-       return &v->shader->const_state;
+       if (v->binning_pass)
+               return v->nonbinning->const_state;
+       return v->const_state;
 }
 
 void * ir3_shader_assemble(struct ir3_shader_variant *v);
@@ -749,8 +770,6 @@ struct ir3_shader_linkage {
 static inline void
 ir3_link_add(struct ir3_shader_linkage *l, uint8_t regid_, uint8_t compmask, uint8_t loc)
 {
-
-
        for (int j = 0; j < util_last_bit(compmask); j++) {
                uint8_t comploc = loc + j;
                l->varmask[comploc / 32] |= 1 << (comploc % 32);