freedreno: update generated headers

[mesa.git] / src / freedreno / registers / a5xx.xml.h

diff --git a/src/freedreno/registers/a5xx.xml.h b/src/freedreno/registers/a5xx.xml.h
index cd9545891d312dfa73464306c72c4f0eb839763c..fc02f90d8e99ba04e0c0f466aa2118d548bcb13b 100644 (file)
--- a/src/freedreno/registers/a5xx.xml.h
+++ b/src/freedreno/registers/a5xx.xml.h
@@ -12,11 +12,11 @@ The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2018-07-03 19:37:13)
 - /home/robclark/src/envytools/rnndb/adreno/a2xx.xml          (  79608 bytes, from 2019-01-21 14:36:17)
 - /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml (  14239 bytes, from 2018-12-05 15:25:53)
-- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml    (  43155 bytes, from 2019-05-03 18:24:29)
+- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml    (  43561 bytes, from 2019-06-10 13:39:33)
 - /home/robclark/src/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2018-07-03 19:37:13)
 - /home/robclark/src/envytools/rnndb/adreno/a4xx.xml          ( 112086 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml          ( 147240 bytes, from 2019-05-03 18:24:29)
-- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml          ( 148461 bytes, from 2019-05-03 18:24:37)
+- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml          ( 147548 bytes, from 2019-06-10 13:39:33)
+- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml          ( 152605 bytes, from 2019-06-11 15:59:35)
 - /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml      (  10431 bytes, from 2018-09-14 13:03:07)
 - /home/robclark/src/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2018-07-03 19:37:13)
 
@@ -2150,6 +2150,8 @@ static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val)
 
 #define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_1                      0x00000e01
 
+#define REG_A5XX_HLSQ_DBG_ECO_CNTL                             0x00000e04
+
 #define REG_A5XX_HLSQ_ADDR_MODE_CNTL                           0x00000e05
 
 #define REG_A5XX_HLSQ_MODE_CNTL                                        0x00000e06
@@ -5222,5 +5224,21 @@ static inline uint32_t A5XX_SSBO_2_1_BASE_HI(uint32_t val)
        return ((val) << A5XX_SSBO_2_1_BASE_HI__SHIFT) & A5XX_SSBO_2_1_BASE_HI__MASK;
 }
 
+#define REG_A5XX_UBO_0                                         0x00000000
+#define A5XX_UBO_0_BASE_LO__MASK                               0xffffffff
+#define A5XX_UBO_0_BASE_LO__SHIFT                              0
+static inline uint32_t A5XX_UBO_0_BASE_LO(uint32_t val)
+{
+       return ((val) << A5XX_UBO_0_BASE_LO__SHIFT) & A5XX_UBO_0_BASE_LO__MASK;
+}
+
+#define REG_A5XX_UBO_1                                         0x00000001
+#define A5XX_UBO_1_BASE_HI__MASK                               0x0001ffff
+#define A5XX_UBO_1_BASE_HI__SHIFT                              0
+static inline uint32_t A5XX_UBO_1_BASE_HI(uint32_t val)
+{
+       return ((val) << A5XX_UBO_1_BASE_HI__SHIFT) & A5XX_UBO_1_BASE_HI__MASK;
+}
+
 
 #endif /* A5XX_XML */