<reg32 offset="0x0630" name="DBGC_CFG_DBGBUS_TRACE_BUF2"/>
<reg32 offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL_0"/>
<reg32 offset="0x0CD9" name="VSC_PERFCTR_VSC_SEL_1"/>
- <reg32 offset="0x8601" name="GRAS_ADDR_MODE_CNTL"/>
- <reg32 offset="0x8610" name="GRAS_PERFCTR_TSE_SEL_0"/>
- <reg32 offset="0x8611" name="GRAS_PERFCTR_TSE_SEL_1"/>
- <reg32 offset="0x8612" name="GRAS_PERFCTR_TSE_SEL_2"/>
- <reg32 offset="0x8613" name="GRAS_PERFCTR_TSE_SEL_3"/>
- <reg32 offset="0x8614" name="GRAS_PERFCTR_RAS_SEL_0"/>
- <reg32 offset="0x8615" name="GRAS_PERFCTR_RAS_SEL_1"/>
- <reg32 offset="0x8616" name="GRAS_PERFCTR_RAS_SEL_2"/>
- <reg32 offset="0x8617" name="GRAS_PERFCTR_RAS_SEL_3"/>
- <reg32 offset="0x8618" name="GRAS_PERFCTR_LRZ_SEL_0"/>
- <reg32 offset="0x8619" name="GRAS_PERFCTR_LRZ_SEL_1"/>
- <reg32 offset="0x861A" name="GRAS_PERFCTR_LRZ_SEL_2"/>
- <reg32 offset="0x861B" name="GRAS_PERFCTR_LRZ_SEL_3"/>
- <reg32 offset="0x8E05" name="RB_ADDR_MODE_CNTL"/>
- <reg32 offset="0x8E08" name="RB_NC_MODE_CNTL"/>
- <reg32 offset="0x8E10" name="RB_PERFCTR_RB_SEL_0"/>
- <reg32 offset="0x8E11" name="RB_PERFCTR_RB_SEL_1"/>
- <reg32 offset="0x8E12" name="RB_PERFCTR_RB_SEL_2"/>
- <reg32 offset="0x8E13" name="RB_PERFCTR_RB_SEL_3"/>
- <reg32 offset="0x8E14" name="RB_PERFCTR_RB_SEL_4"/>
- <reg32 offset="0x8E15" name="RB_PERFCTR_RB_SEL_5"/>
- <reg32 offset="0x8E16" name="RB_PERFCTR_RB_SEL_6"/>
- <reg32 offset="0x8E17" name="RB_PERFCTR_RB_SEL_7"/>
- <reg32 offset="0x8E18" name="RB_PERFCTR_CCU_SEL_0"/>
- <reg32 offset="0x8E19" name="RB_PERFCTR_CCU_SEL_1"/>
- <reg32 offset="0x8E1A" name="RB_PERFCTR_CCU_SEL_2"/>
- <reg32 offset="0x8E1B" name="RB_PERFCTR_CCU_SEL_3"/>
- <reg32 offset="0x8E1C" name="RB_PERFCTR_CCU_SEL_4"/>
- <reg32 offset="0x8E2C" name="RB_PERFCTR_CMP_SEL_0"/>
- <reg32 offset="0x8E2D" name="RB_PERFCTR_CMP_SEL_1"/>
- <reg32 offset="0x8E2E" name="RB_PERFCTR_CMP_SEL_2"/>
- <reg32 offset="0x8E2F" name="RB_PERFCTR_CMP_SEL_3"/>
- <reg32 offset="0x8E3D" name="RB_RB_SUB_BLOCK_SEL_CNTL_CD"/>
- <reg32 offset="0x8E50" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE"/>
- <reg32 offset="0x9E00" name="PC_DBG_ECO_CNTL"/>
- <reg32 offset="0x9E01" name="PC_ADDR_MODE_CNTL"/>
- <reg32 offset="0x9E34" name="PC_PERFCTR_PC_SEL_0"/>
- <reg32 offset="0x9E35" name="PC_PERFCTR_PC_SEL_1"/>
- <reg32 offset="0x9E36" name="PC_PERFCTR_PC_SEL_2"/>
- <reg32 offset="0x9E37" name="PC_PERFCTR_PC_SEL_3"/>
- <reg32 offset="0x9E38" name="PC_PERFCTR_PC_SEL_4"/>
- <reg32 offset="0x9E39" name="PC_PERFCTR_PC_SEL_5"/>
- <reg32 offset="0x9E3A" name="PC_PERFCTR_PC_SEL_6"/>
- <reg32 offset="0x9E3B" name="PC_PERFCTR_PC_SEL_7"/>
<reg32 offset="0xBE05" name="HLSQ_ADDR_MODE_CNTL"/>
<reg32 offset="0xBE10" name="HLSQ_PERFCTR_HLSQ_SEL_0"/>
<reg32 offset="0xBE11" name="HLSQ_PERFCTR_HLSQ_SEL_1"/>
<reg32 offset="0xA615" name="VFD_PERFCTR_VFD_SEL_5"/>
<reg32 offset="0xA616" name="VFD_PERFCTR_VFD_SEL_6"/>
<reg32 offset="0xA617" name="VFD_PERFCTR_VFD_SEL_7"/>
- <reg32 offset="0x9601" name="VPC_ADDR_MODE_CNTL"/>
- <reg32 offset="0x9604" name="VPC_PERFCTR_VPC_SEL_0"/>
- <reg32 offset="0x9605" name="VPC_PERFCTR_VPC_SEL_1"/>
- <reg32 offset="0x9606" name="VPC_PERFCTR_VPC_SEL_2"/>
- <reg32 offset="0x9607" name="VPC_PERFCTR_VPC_SEL_3"/>
- <reg32 offset="0x9608" name="VPC_PERFCTR_VPC_SEL_4"/>
- <reg32 offset="0x9609" name="VPC_PERFCTR_VPC_SEL_5"/>
<reg32 offset="0x0E00" name="UCHE_ADDR_MODE_CNTL"/>
<reg32 offset="0x0E01" name="UCHE_MODE_CNTL"/>
<reg32 offset="0x0E05" name="UCHE_WRITE_RANGE_MAX_LO"/>
<!-- move/rename these.. -->
- <reg32 offset="0x88d4" name="RB_WINDOW_OFFSET2" type="adreno_reg_xy"/>
<reg32 offset="0xb4d1" name="SP_WINDOW_OFFSET" type="adreno_reg_xy"/>
<reg32 offset="0xb307" name="SP_TP_WINDOW_OFFSET" type="adreno_reg_xy"/>
- <!-- same as RB_BIN_CONTROL -->
- <reg32 offset="0x80a1" name="GRAS_BIN_CONTROL">
- <bitfield name="BINW" low="0" high="7" shr="5" type="uint"/>
- <bitfield name="BINH" low="8" high="16" shr="4" type="uint"/>
- <bitfield name="BINNING_PASS" pos="18" type="boolean"/>
- <bitfield name="USE_VIZ" pos="21" type="boolean"/>
- </reg32>
-
- <!--
- from offset it seems it should be RB, but weird to duplicate
- other regs from same block??
- -->
- <reg32 offset="0x88d3" name="RB_BIN_CONTROL2">
- <bitfield name="BINW" low="0" high="7" shr="5" type="uint"/>
- <bitfield name="BINH" low="8" high="16" shr="4" type="uint"/>
- </reg32>
-
<reg32 offset="0x0c02" name="VSC_BIN_SIZE">
<bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/>
<bitfield name="HEIGHT" low="8" high="16" shr="4" type="uint"/>
<!-- always 0x03200000 ? -->
<reg32 offset="0x0e12" name="UCHE_UNKNOWN_0E12"/>
+ <!-- adreno_reg_xy has 15 bits per coordinate, but a6xx registers only have 14 -->
+ <bitset name="a6xx_reg_xy" inline="yes">
+ <bitfield name="X" low="0" high="13" type="uint"/>
+ <bitfield name="Y" low="16" high="29" type="uint"/>
+ </bitset>
+
<reg32 offset="0x8000" name="GRAS_CL_CNTL">
<bitfield name="CLIP_DISABLE" pos="0" type="boolean"/>
<bitfield name="ZNEAR_CLIP_DISABLE" pos="1" type="boolean"/>
<bitfield name="VP_XFORM_DISABLE" pos="8" type="boolean"/>
<bitfield name="PERSP_DIVISION_DISABLE" pos="9" type="boolean"/>
</reg32>
+
<bitset name="a6xx_gras_xs_cl_cntl" inline="yes">
<bitfield name="CLIP_MASK" low="0" high="7"/>
<bitfield name="CULL_MASK" low="8" high="15"/>
<reg32 offset="0x8001" name="GRAS_VS_CL_CNTL" type="a6xx_gras_xs_cl_cntl"/>
<reg32 offset="0x8002" name="GRAS_DS_CL_CNTL" type="a6xx_gras_xs_cl_cntl"/>
<reg32 offset="0x8003" name="GRAS_GS_CL_CNTL" type="a6xx_gras_xs_cl_cntl"/>
-
- <enum name="a6xx_layer_type">
- <value value="0x0" name="LAYER_MULTISAMPLE_ARRAY"/>
- <value value="0x1" name="LAYER_3D"/>
- <value value="0x2" name="LAYER_CUBEMAP"/>
- <value value="0x3" name="LAYER_2D_ARRAY"/>
- </enum>
-
- <!-- index of highest layer that can be written to via gl_Layer -->
- <reg32 offset="0x8004" name="GRAS_MAX_LAYER_INDEX" type="uint"/>
+ <reg32 offset="0x8004" name="GRAS_MAX_LAYER_INDEX" low="0" high="10" type="uint"/>
<reg32 offset="0x8005" name="GRAS_CNTL">
<!-- see also RB_RENDER_CONTROL0 -->
mode, and frag_face
-->
<bitfield name="SIZE" pos="3" type="boolean"/>
+ <bitfield name="UNK4" pos="4" type="boolean"/>
<!-- b5 set ofr interpolateAt{Offset,Sample}() if in per-sample mode -->
<bitfield name="SIZE_PERSAMP" pos="5" type="boolean"/>
<bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
</reg32>
<reg32 offset="0x8006" name="GRAS_CL_GUARDBAND_CLIP_ADJ">
- <bitfield name="HORZ" low="0" high="9" type="uint"/>
- <bitfield name="VERT" low="10" high="19" type="uint"/>
- </reg32>
- <reg32 offset="0x8010" name="GRAS_CL_VPORT_XOFFSET_0" type="float"/>
- <reg32 offset="0x8011" name="GRAS_CL_VPORT_XSCALE_0" type="float"/>
- <reg32 offset="0x8012" name="GRAS_CL_VPORT_YOFFSET_0" type="float"/>
- <reg32 offset="0x8013" name="GRAS_CL_VPORT_YSCALE_0" type="float"/>
- <reg32 offset="0x8014" name="GRAS_CL_VPORT_ZOFFSET_0" type="float"/>
- <reg32 offset="0x8015" name="GRAS_CL_VPORT_ZSCALE_0" type="float"/>
-
- <!-- not clear what it does, mirrors RB_Z_CLAMP_MIN -->
- <reg32 offset="0x8070" name="GRAS_CL_Z_CLAMP_MIN" type="float"/>
- <reg32 offset="0x8071" name="GRAS_CL_Z_CLAMP_MAX" type="float"/>
+ <bitfield name="HORZ" low="0" high="8" type="uint"/>
+ <bitfield name="VERT" low="10" high="18" type="uint"/>
+ </reg32>
+ <!-- 0x8006-0x800f invalid -->
+ <array offset="0x8010" name="GRAS_CL_VPORT" stride="6" length="16">
+ <reg32 offset="0" name="XOFFSET" type="float"/>
+ <reg32 offset="1" name="XSCALE" type="float"/>
+ <reg32 offset="2" name="YOFFSET" type="float"/>
+ <reg32 offset="3" name="YSCALE" type="float"/>
+ <reg32 offset="4" name="ZOFFSET" type="float"/>
+ <reg32 offset="5" name="ZSCALE" type="float"/>
+ </array>
+ <array offset="0x8070" name="GRAS_CL_Z_CLAMP" stride="2" length="16">
+ <reg32 offset="0" name="MIN" type="float"/>
+ <reg32 offset="1" name="MAX" type="float"/>
+ </array>
<reg32 offset="0x8090" name="GRAS_SU_CNTL">
<bitfield name="CULL_FRONT" pos="0" type="boolean"/>
<bitfield name="FRONT_CW" pos="2" type="boolean"/>
<bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>
<bitfield name="POLY_OFFSET" pos="11" type="boolean"/>
+ <bitfield name="UNK12" pos="12"/>
<bitfield name="MSAA_ENABLE" pos="13" type="boolean"/>
- <!-- probably LINEHALFWIDTH is the same as a4xx.. -->
+ <bitfield name="UNK15" low="15" high="22"/>
</reg32>
<reg32 offset="0x8091" name="GRAS_SU_POINT_MINMAX">
<bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
<bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
</reg32>
- <reg32 offset="0x8092" name="GRAS_SU_POINT_SIZE" type="fixed" radix="4"/>
-
+ <reg32 offset="0x8092" name="GRAS_SU_POINT_SIZE" low="0" high="15" type="fixed" radix="4"/>
+ <!-- 0x8093 invalid -->
<reg32 offset="0x8094" name="GRAS_SU_DEPTH_PLANE_CNTL">
<bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/>
</reg32>
<!-- duplicates RB_DEPTH_BUFFER_INFO: -->
<reg32 offset="0x8098" name="GRAS_SU_DEPTH_BUFFER_INFO">
<bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
+ <bitfield name="UNK3" pos="3"/>
</reg32>
- <!-- always 0x0 -->
- <reg32 offset="0x8099" name="GRAS_UNKNOWN_8099"/>
+ <reg32 offset="0x8099" name="GRAS_UNKNOWN_8099" low="0" high="5"/>
+ <reg32 offset="0x809a" name="GRAS_UNKNOWN_809A" low="0" high="1"/>
<bitset name="a6xx_gras_layer_cntl" inline="yes">
<bitfield name="WRITES_LAYER" pos="0" type="boolean"/>
+ <bitfield name="WRITES_VIEW" pos="1" type="boolean"/>
</bitset>
<reg32 offset="0x809b" name="GRAS_VS_LAYER_CNTL" type="a6xx_gras_layer_cntl"/>
<reg32 offset="0x809c" name="GRAS_GS_LAYER_CNTL" type="a6xx_gras_layer_cntl"/>
<reg32 offset="0x809d" name="GRAS_DS_LAYER_CNTL" type="a6xx_gras_layer_cntl"/>
-
- <reg32 offset="0x80a0" name="GRAS_UNKNOWN_80A0"/>
+ <!-- 0x809e/0x809f invalid -->
+ <reg32 offset="0x80a0" name="GRAS_UNKNOWN_80A0" low="0" high="12"/>
+ <reg32 offset="0x80a1" name="GRAS_BIN_CONTROL">
+ <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
+ <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
+ <bitfield name="BINNING_PASS" pos="18" type="boolean"/>
+ <bitfield name="UNK19" pos="19"/>
+ <bitfield name="UNK20" pos="20"/>
+ <bitfield name="USE_VIZ" pos="21" type="boolean"/>
+ <bitfield name="UNK22" low="22" high="27"/>
+ </reg32>
<reg32 offset="0x80a2" name="GRAS_RAS_MSAA_CNTL">
<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
+ <bitfield name="UNK2" pos="2"/>
+ <bitfield name="UNK3" pos="3"/>
</reg32>
<reg32 offset="0x80a3" name="GRAS_DEST_MSAA_CNTL">
<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
</reg32>
<bitset name="a6xx_sample_config" inline="yes">
+ <bitfield name="UNK0" pos="0"/>
<bitfield name="LOCATION_ENABLE" pos="1" type="boolean"/>
</bitset>
<reg32 offset="0x80a4" name="GRAS_SAMPLE_CONFIG" type="a6xx_sample_config"/>
<reg32 offset="0x80a5" name="GRAS_SAMPLE_LOCATION_0" type="a6xx_sample_locations"/>
<reg32 offset="0x80a6" name="GRAS_SAMPLE_LOCATION_1" type="a6xx_sample_locations"/>
+ <!-- 0x80a7-0x80ae invalid -->
+ <reg32 offset="0x80af" name="GRAS_UNKNOWN_80AF" pos="0"/>
- <!-- always 0x0 -->
- <reg32 offset="0x80af" name="GRAS_UNKNOWN_80AF"/>
+ <bitset name="a6xx_scissor_xy" inline="yes">
+ <bitfield name="X" low="0" high="15" type="uint"/>
+ <bitfield name="Y" low="16" high="31" type="uint"/>
+ </bitset>
+ <array offset="0x80b0" name="GRAS_SC_SCREEN_SCISSOR" stride="2" length="16">
+ <reg32 offset="0" name="TL" type="a6xx_scissor_xy"/>
+ <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/>
+ </array>
+ <array offset="0x80d0" name="GRAS_SC_VIEWPORT_SCISSOR" stride="2" length="16">
+ <reg32 offset="0" name="TL" type="a6xx_scissor_xy"/>
+ <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/>
+ </array>
- <reg32 offset="0x80b0" name="GRAS_SC_SCREEN_SCISSOR_TL_0" type="adreno_reg_xy"/>
- <reg32 offset="0x80b1" name="GRAS_SC_SCREEN_SCISSOR_BR_0" type="adreno_reg_xy"/>
- <reg32 offset="0x80d0" name="GRAS_SC_VIEWPORT_SCISSOR_TL_0" type="adreno_reg_xy"/>
- <reg32 offset="0x80d1" name="GRAS_SC_VIEWPORT_SCISSOR_BR_0" type="adreno_reg_xy"/>
- <reg32 offset="0x80f0" name="GRAS_SC_WINDOW_SCISSOR_TL" type="adreno_reg_xy"/>
- <reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="adreno_reg_xy"/>
+ <reg32 offset="0x80f0" name="GRAS_SC_WINDOW_SCISSOR_TL" type="a6xx_reg_xy"/>
+ <reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="a6xx_reg_xy"/>
+ <!-- 0x80f2-0x80ff invalid -->
<reg32 offset="0x8100" name="GRAS_LRZ_CNTL">
<!--
<bitfield name="FC_ENABLE" pos="3" type="boolean"/>
<!-- set when depth-test + depth-write enabled -->
<bitfield name="Z_TEST_ENABLE" pos="4" type="boolean"/>
+ <bitfield name="UNK5" low="5" high="9"/>
</reg32>
- <reg32 offset="0x8101" name="GRAS_UNKNOWN_8101"/>
+ <reg32 offset="0x8101" name="GRAS_UNKNOWN_8101" low="0" high="2"/>
<reg32 offset="0x8102" name="GRAS_2D_BLIT_INFO">
<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
</reg32>
<reg32 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE_LO"/>
<reg32 offset="0x8104" name="GRAS_LRZ_BUFFER_BASE_HI"/>
- <reg64 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE" type="waddress"/>
+ <reg64 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE" align="256" type="waddress"/>
<reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH">
- <bitfield name="PITCH" low="0" high="10" shr="5" type="uint"/>
- <bitfield name="ARRAY_PITCH" low="11" high="21" shr="5" type="uint"/> <!-- ??? -->
+ <!-- TODO: fix the shr fields -->
+ <bitfield name="PITCH" low="0" high="7" shr="5" type="uint"/>
+ <bitfield name="ARRAY_PITCH" low="10" high="28" shr="4" type="uint"/>
</reg32>
<!--
-->
<reg32 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO"/>
<reg32 offset="0x8107" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI"/>
- <reg32 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE" type="waddress"/>
-
+ <reg32 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE" align="64" type="waddress"/>
+ <!-- 0x8108 invalid -->
<reg32 offset="0x8109" name="GRAS_SAMPLE_CNTL">
<bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
</reg32>
+ <reg32 offset="0x810a" name="GRAS_UNKNOWN_810A">
+ <bitfield name="UNK0" low="0" high="10" type="uint"/>
+ <bitfield name="UNK16" low="16" high="26" type="uint"/>
+ <bitfield name="UNK28" low="28" high="31" type="uint"/>
+ </reg32>
+
+ <!-- 0x810b-0x810f invalid -->
- <reg32 offset="0x8110" name="GRAS_UNKNOWN_8110"/>
+ <reg32 offset="0x8110" name="GRAS_UNKNOWN_8110" low="0" high="1"/>
+
+ <!-- 0x8111-0x83ff invalid -->
<enum name="a6xx_rotation">
- <value value="0x0" name="ROTATE_0"/>
- <value value="0x1" name="ROTATE_90"/>
- <value value="0x2" name="ROTATE_180"/>
- <value value="0x3" name="ROTATE_270"/>
- <value value="0x4" name="ROTATE_HFLIP"/>
- <value value="0x5" name="ROTATE_VFLIP"/>
+ <value value="0x0" name="ROTATE_0"/>
+ <value value="0x1" name="ROTATE_90"/>
+ <value value="0x2" name="ROTATE_180"/>
+ <value value="0x3" name="ROTATE_270"/>
+ <value value="0x4" name="ROTATE_HFLIP"/>
+ <value value="0x5" name="ROTATE_VFLIP"/>
</enum>
<bitset name="a6xx_2d_blit_cntl" inline="yes">
<bitfield name="ROTATE" low="0" high="2" type="a6xx_rotation"/>
+ <bitfield name="UNK3" low="3" high="6"/>
<bitfield name="SOLID_COLOR" pos="7" type="boolean"/>
<bitfield name="COLOR_FORMAT" low="8" high="15" type="a6xx_format"/>
<bitfield name="SCISSOR" pos="16" type="boolean"/>
-
- <bitfield name="UNK" low="17" high="18" type="uint"/>
-
+ <bitfield name="UNK17" low="17" high="18"/>
<!-- required when blitting D24S8/D24X8 -->
<bitfield name="D24S8" pos="19" type="boolean"/>
<!-- some sort of channel mask, disabled channels are set to zero ? -->
<bitfield name="MASK" low="20" high="23"/>
<bitfield name="IFMT" low="24" high="28" type="a6xx_2d_ifmt"/>
+ <bitfield name="UNK29" pos="29"/>
</bitset>
<reg32 offset="0x8400" name="GRAS_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl"/>
+ <!-- note: the low 8 bits for src coords are valid, probably fixed point
+ it would be a bit weird though, since we subtract 1 from BR coords
+ apparently signed, gallium driver uses negative coords and it works?
+ -->
+ <reg32 offset="0x8401" name="GRAS_2D_SRC_TL_X" low="8" high="24" type="int"/>
+ <reg32 offset="0x8402" name="GRAS_2D_SRC_BR_X" low="8" high="24" type="int"/>
+ <reg32 offset="0x8403" name="GRAS_2D_SRC_TL_Y" low="8" high="24" type="int"/>
+ <reg32 offset="0x8404" name="GRAS_2D_SRC_BR_Y" low="8" high="24" type="int"/>
+ <reg32 offset="0x8405" name="GRAS_2D_DST_TL" type="a6xx_reg_xy"/>
+ <reg32 offset="0x8406" name="GRAS_2D_DST_BR" type="a6xx_reg_xy"/>
+ <reg32 offset="0x8407" name="GRAS_2D_UNKNOWN_8407" low="0" high="31"/>
+ <reg32 offset="0x8408" name="GRAS_2D_UNKNOWN_8408" low="0" high="31"/>
+ <reg32 offset="0x8409" name="GRAS_2D_UNKNOWN_8409" low="0" high="31"/>
+ <reg32 offset="0x840a" name="GRAS_2D_RESOLVE_CNTL_1" type="a6xx_reg_xy"/>
+ <reg32 offset="0x840b" name="GRAS_2D_RESOLVE_CNTL_2" type="a6xx_reg_xy"/>
+ <!-- 0x840c-0x85ff invalid -->
+
+ <!-- always 0x880 ? (and 0 in a640/a650 traces?) -->
+ <reg32 offset="0x8600" name="GRAS_UNKNOWN_8600" low="0" high="12" />
+ <reg32 offset="0x8601" name="GRAS_ADDR_MODE_CNTL" pos="0" type="boolean"/>
+ <reg32 offset="0x8610" name="GRAS_PERFCTR_TSE_SEL_0"/>
+ <reg32 offset="0x8611" name="GRAS_PERFCTR_TSE_SEL_1"/>
+ <reg32 offset="0x8612" name="GRAS_PERFCTR_TSE_SEL_2"/>
+ <reg32 offset="0x8613" name="GRAS_PERFCTR_TSE_SEL_3"/>
+ <reg32 offset="0x8614" name="GRAS_PERFCTR_RAS_SEL_0"/>
+ <reg32 offset="0x8615" name="GRAS_PERFCTR_RAS_SEL_1"/>
+ <reg32 offset="0x8616" name="GRAS_PERFCTR_RAS_SEL_2"/>
+ <reg32 offset="0x8617" name="GRAS_PERFCTR_RAS_SEL_3"/>
+ <reg32 offset="0x8618" name="GRAS_PERFCTR_LRZ_SEL_0"/>
+ <reg32 offset="0x8619" name="GRAS_PERFCTR_LRZ_SEL_1"/>
+ <reg32 offset="0x861A" name="GRAS_PERFCTR_LRZ_SEL_2"/>
+ <reg32 offset="0x861B" name="GRAS_PERFCTR_LRZ_SEL_3"/>
- <!-- could be the src coords are fixed point? -->
- <reg32 offset="0x8401" name="GRAS_2D_SRC_TL_X">
- <bitfield name="X" low="8" high="31" type="int"/>
- </reg32>
- <reg32 offset="0x8402" name="GRAS_2D_SRC_BR_X">
- <bitfield name="X" low="8" high="31" type="int"/>
- </reg32>
- <reg32 offset="0x8403" name="GRAS_2D_SRC_TL_Y">
- <bitfield name="Y" low="8" high="31" type="int"/>
- </reg32>
- <reg32 offset="0x8404" name="GRAS_2D_SRC_BR_Y">
- <bitfield name="Y" low="8" high="31" type="int"/>
- </reg32>
-
- <reg32 offset="0x8405" name="GRAS_2D_DST_TL" type="adreno_reg_xy"/>
- <reg32 offset="0x8406" name="GRAS_2D_DST_BR" type="adreno_reg_xy"/>
-
- <reg32 offset="0x840a" name="GRAS_RESOLVE_CNTL_1" type="adreno_reg_xy"/>
- <reg32 offset="0x840b" name="GRAS_RESOLVE_CNTL_2" type="adreno_reg_xy"/>
-
- <!-- always 0x880 ? -->
- <reg32 offset="0x8600" name="GRAS_UNKNOWN_8600"/>
+ <!-- note 0x8620-0x87ff are not all invalid
+ (in particular, 0x8631/0x8632 have 0x3fff3fff mask and would be xy coords)
+ -->
- <!-- same as GRAS_BIN_CONTROL: -->
+ <!-- same as GRAS_BIN_CONTROL, but without bit 27: -->
<reg32 offset="0x8800" name="RB_BIN_CONTROL">
- <bitfield name="BINW" low="0" high="7" shr="5" type="uint"/>
- <bitfield name="BINH" low="8" high="16" shr="4" type="uint"/>
+ <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
+ <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
<bitfield name="BINNING_PASS" pos="18" type="boolean"/>
+ <bitfield name="UNK19" pos="19"/>
+ <bitfield name="UNK20" pos="20"/>
<bitfield name="USE_VIZ" pos="21" type="boolean"/>
+ <bitfield name="UNK22" low="22" high="26"/>
</reg32>
<reg32 offset="0x8801" name="RB_RENDER_CNTL">
+ <bitfield name="UNK3" pos="3" type="boolean"/>
<!-- always set: ?? -->
<bitfield name="UNK4" pos="4" type="boolean"/>
+ <bitfield name="UNK5" low="5" high="6"/>
<!-- set during binning pass: -->
<bitfield name="BINNING" pos="7" type="boolean"/>
+ <bitfield name="UNK8" low="8" high="12"/>
<!-- bit seems to be set whenever depth buffer enabled: -->
<bitfield name="FLAG_DEPTH" pos="14" type="boolean"/>
<!-- bitmask of MRTs using UBWC flag buffer: -->
</reg32>
<reg32 offset="0x8802" name="RB_RAS_MSAA_CNTL">
<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
+ <bitfield name="UNK2" pos="2"/>
+ <bitfield name="UNK3" pos="3"/>
</reg32>
<reg32 offset="0x8803" name="RB_DEST_MSAA_CNTL">
<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
<reg32 offset="0x8804" name="RB_SAMPLE_CONFIG" type="a6xx_sample_config"/>
<reg32 offset="0x8805" name="RB_SAMPLE_LOCATION_0" type="a6xx_sample_locations"/>
<reg32 offset="0x8806" name="RB_SAMPLE_LOCATION_1" type="a6xx_sample_locations"/>
-
+ <!-- 0x8807-0x8808 invalid -->
<!--
note: maybe not actually called RB_RENDER_CONTROLn (since RB_RENDER_CNTL
name comes from kernel and is probably right)
mode, and frag_face
-->
<bitfield name="SIZE" pos="3" type="boolean"/>
+ <bitfield name="UNK4" pos="4" type="boolean"/>
<!-- b5 set ofr interpolateAt{Offset,Sample}() if in per-sample mode -->
<bitfield name="SIZE_PERSAMP" pos="5" type="boolean"/>
<bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
<reg32 offset="0x880a" name="RB_RENDER_CONTROL1">
<!-- enable bits for various FS sysvalue regs: -->
<bitfield name="SAMPLEMASK" pos="0" type="boolean"/>
+ <bitfield name="UNK1" pos="1" type="boolean"/>
<bitfield name="FACENESS" pos="2" type="boolean"/>
<bitfield name="SAMPLEID" pos="3" type="boolean"/>
<!-- b4 and b5 set in per-sample mode: -->
<bitfield name="UNK4" pos="4" type="boolean"/>
<bitfield name="UNK5" pos="5" type="boolean"/>
<bitfield name="SIZE" pos="6" type="boolean"/>
+ <bitfield name="UNK7" pos="7" type="boolean"/>
+ <bitfield name="UNK8" pos="8" type="boolean"/>
</reg32>
<reg32 offset="0x880b" name="RB_FS_OUTPUT_CNTL0">
<bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>
<bitfield name="FRAG_WRITES_Z" pos="1" type="boolean"/>
<bitfield name="FRAG_WRITES_SAMPMASK" pos="2" type="boolean"/>
+ <bitfield name="FRAG_WRITES_STENCILREF" pos="3" type="boolean"/>
</reg32>
<reg32 offset="0x880c" name="RB_FS_OUTPUT_CNTL1">
<bitfield name="MRT" low="0" high="3" type="uint"/>
<reg32 offset="0x8810" name="RB_SAMPLE_CNTL">
<bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
</reg32>
- <reg32 offset="0x8811" name="RB_UNKNOWN_8811"/>
-
+ <reg32 offset="0x8811" name="RB_UNKNOWN_8811" low="4" high="6"/>
+ <!-- 0x8812-0x8817 invalid -->
<!-- always 0x0 ? -->
- <reg32 offset="0x8818" name="RB_UNKNOWN_8818"/>
+ <reg32 offset="0x8818" name="RB_UNKNOWN_8818" low="0" high="6"/>
+ <!-- 0x8819-0x881e all 32 bits -->
<reg32 offset="0x8819" name="RB_UNKNOWN_8819"/>
<reg32 offset="0x881a" name="RB_UNKNOWN_881A"/>
<reg32 offset="0x881b" name="RB_UNKNOWN_881B"/>
<reg32 offset="0x881c" name="RB_UNKNOWN_881C"/>
<reg32 offset="0x881d" name="RB_UNKNOWN_881D"/>
<reg32 offset="0x881e" name="RB_UNKNOWN_881E"/>
-
+ <!-- 0x881f invalid -->
<array offset="0x8820" name="RB_MRT" stride="8" length="8">
<reg32 offset="0x0" name="CONTROL">
<bitfield name="BLEND" pos="0" type="boolean"/>
<reg32 offset="0x2" name="BUF_INFO">
<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
<bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
+ <bitfield name="UNK10" pos="10"/>
<bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/>
</reg32>
<!--
at least in gmem, things seem to be aligned to pitch of 64..
maybe an artifact of tiled format used in gmem?
-->
- <reg32 offset="0x3" name="PITCH" shr="6" type="uint"/>
- <reg32 offset="0x4" name="ARRAY_PITCH" shr="6" type="uint"/>
+ <reg32 offset="0x3" name="PITCH" shr="6" high="15" type="uint"/>
+ <reg32 offset="0x4" name="ARRAY_PITCH" shr="6" high="28" type="uint"/>
<!--
Compared to a5xx and before, we configure both a GMEM base and
external base. Not sure if this is to facilitate GMEM save/
<reg32 offset="0x5" name="BASE_LO"/>
<reg32 offset="0x6" name="BASE_HI"/>
- <reg64 offset="0x5" name="BASE" type="waddress"/>
+ <!-- maybe something in low bits since alignment of 1 doesn't make sense? -->
+ <reg64 offset="0x5" name="BASE" type="waddress" align="1"/>
- <reg32 offset="0x7" name="BASE_GMEM"/>
+ <reg32 offset="0x7" name="BASE_GMEM" low="12" high="31" shr="12"/>
</array>
<reg32 offset="0x8860" name="RB_BLEND_RED_F32" type="float"/>
<bitfield name="ALPHA_TO_ONE" pos="11" type="boolean"/>
<bitfield name="SAMPLE_MASK" low="16" high="31"/>
</reg32>
+ <!-- 0x8866-0x886f invalid -->
<reg32 offset="0x8870" name="RB_DEPTH_PLANE_CNTL">
<bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/>
</reg32>
<!-- duplicates GRAS_SU_DEPTH_BUFFER_INFO: -->
<reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO">
<bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
+ <bitfield name="UNK3" low="3" high="4"/>
</reg32>
-<!-- probably: -->
- <reg32 offset="0x8873" name="RB_DEPTH_BUFFER_PITCH" shr="6" type="uint">
- <doc>stride of depth/stencil buffer</doc>
- </reg32>
- <reg32 offset="0x8874" name="RB_DEPTH_BUFFER_ARRAY_PITCH" shr="6" type="uint">
- <doc>size of layer</doc>
- </reg32>
+ <reg32 offset="0x8873" name="RB_DEPTH_BUFFER_PITCH" low="0" high="13" shr="6" type="uint"/>
+ <reg32 offset="0x8874" name="RB_DEPTH_BUFFER_ARRAY_PITCH" low="0" high="27" shr="6" type="uint"/>
<reg32 offset="0x8875" name="RB_DEPTH_BUFFER_BASE_LO"/>
<reg32 offset="0x8876" name="RB_DEPTH_BUFFER_BASE_HI"/>
- <reg64 offset="0x8875" name="RB_DEPTH_BUFFER_BASE" type="waddress"/>
- <reg32 offset="0x8877" name="RB_DEPTH_BUFFER_BASE_GMEM"/>
+ <reg64 offset="0x8875" name="RB_DEPTH_BUFFER_BASE" type="waddress" align="64"/>
+ <reg32 offset="0x8877" name="RB_DEPTH_BUFFER_BASE_GMEM" low="12" high="31" shr="12"/>
<reg32 offset="0x8878" name="RB_Z_BOUNDS_MIN" type="float"/>
<reg32 offset="0x8879" name="RB_Z_BOUNDS_MAX" type="float"/>
-
+ <!-- 0x887a-0x887f invalid -->
<reg32 offset="0x8880" name="RB_STENCIL_CONTROL">
<bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
<bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/>
</reg32>
<reg32 offset="0x8881" name="RB_STENCIL_INFO">
<bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/>
+ <bitfield name="UNK1" pos="1" type="boolean"/>
</reg32>
- <reg32 offset="0x8882" name="RB_STENCIL_BUFFER_PITCH" shr="6" type="uint">
- <doc>stride of stencil buffer</doc>
- </reg32>
- <reg32 offset="0x8883" name="RB_STENCIL_BUFFER_ARRAY_PITCH" shr="6" type="uint">
- <doc>size of layer</doc>
- </reg32>
+ <reg32 offset="0x8882" name="RB_STENCIL_BUFFER_PITCH" low="0" high="11" shr="6" type="uint"/>
+ <reg32 offset="0x8883" name="RB_STENCIL_BUFFER_ARRAY_PITCH" low="0" high="23" shr="6" type="uint"/>
<reg32 offset="0x8884" name="RB_STENCIL_BUFFER_BASE_LO"/>
<reg32 offset="0x8885" name="RB_STENCIL_BUFFER_BASE_HI"/>
- <reg64 offset="0x8884" name="RB_STENCIL_BUFFER_BASE" type="waddress"/>
- <reg32 offset="0x8886" name="RB_STENCIL_BUFFER_BASE_GMEM"/>
+ <reg64 offset="0x8884" name="RB_STENCIL_BUFFER_BASE" type="waddress" align="64"/>
+ <reg32 offset="0x8886" name="RB_STENCIL_BUFFER_BASE_GMEM" low="12" high="31" shr="12"/>
<reg32 offset="0x8887" name="RB_STENCILREF">
<bitfield name="REF" low="0" high="7"/>
<bitfield name="BFREF" low="8" high="15"/>
<bitfield name="WRMASK" low="0" high="7"/>
<bitfield name="BFWRMASK" low="8" high="15"/>
</reg32>
- <reg32 offset="0x8890" name="RB_WINDOW_OFFSET" type="adreno_reg_xy"/>
+ <!-- 0x888a-0x888f invalid -->
+ <reg32 offset="0x8890" name="RB_WINDOW_OFFSET" type="a6xx_reg_xy"/>
<reg32 offset="0x8891" name="RB_SAMPLE_COUNT_CONTROL">
+ <bitfield name="UNK0" pos="0" type="boolean"/>
<bitfield name="COPY" pos="1" type="boolean"/>
</reg32>
-
+ <!-- 0x8892-0x8897 invalid -->
<reg32 offset="0x8898" name="RB_LRZ_CNTL">
<bitfield name="ENABLE" pos="0" type="boolean"/>
</reg32>
-
+ <!-- 0x8899-0x88bf invalid -->
<!-- clamps depth value for depth test/write -->
<reg32 offset="0x88c0" name="RB_Z_CLAMP_MIN" type="float"/>
<reg32 offset="0x88c1" name="RB_Z_CLAMP_MAX" type="float"/>
-
- <reg32 offset="0x88d0" name="RB_UNKNOWN_88D0"/>
- <reg32 offset="0x88d1" name="RB_BLIT_SCISSOR_TL" type="adreno_reg_xy"/>
- <reg32 offset="0x88d2" name="RB_BLIT_SCISSOR_BR" type="adreno_reg_xy"/>
-
+ <!-- 0x88c2-0x88cf invalid-->
+ <reg32 offset="0x88d0" name="RB_UNKNOWN_88D0">
+ <bitfield name="UNK0" low="0" high="12"/>
+ <bitfield name="UNK16" low="16" high="26"/>
+ </reg32>
+ <reg32 offset="0x88d1" name="RB_BLIT_SCISSOR_TL" type="a6xx_reg_xy"/>
+ <reg32 offset="0x88d2" name="RB_BLIT_SCISSOR_BR" type="a6xx_reg_xy"/>
+ <!-- weird to duplicate other regs from same block?? -->
+ <reg32 offset="0x88d3" name="RB_BIN_CONTROL2">
+ <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
+ <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
+ </reg32>
+ <reg32 offset="0x88d4" name="RB_WINDOW_OFFSET2" type="a6xx_reg_xy"/>
<reg32 offset="0x88d5" name="RB_MSAA_CNTL">
<bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
</reg32>
- <reg32 offset="0x88d6" name="RB_BLIT_BASE_GMEM"/>
+ <reg32 offset="0x88d6" name="RB_BLIT_BASE_GMEM" low="12" high="31" shr="12"/>
<!-- s/DST_FORMAT/DST_INFO/ probably: -->
<reg32 offset="0x88d7" name="RB_BLIT_DST_INFO">
<bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
<bitfield name="FLAGS" pos="2" type="boolean"/>
<bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
- <bitfield name="COLOR_FORMAT" low="7" high="14" type="a6xx_format"/>
<bitfield name="COLOR_SWAP" low="5" high="6" type="a3xx_color_swap"/>
+ <bitfield name="COLOR_FORMAT" low="7" high="14" type="a6xx_format"/>
+ <bitfield name="UNK15" pos="15" type="boolean"/>
</reg32>
- <reg64 offset="0x88d8" name="RB_BLIT_DST" type="waddress"/>
+ <reg64 offset="0x88d8" name="RB_BLIT_DST" type="waddress" align="64"/>
<reg32 offset="0x88d8" name="RB_BLIT_DST_LO"/>
<reg32 offset="0x88d9" name="RB_BLIT_DST_HI"/>
- <reg32 offset="0x88da" name="RB_BLIT_DST_PITCH" shr="6" type="uint"/>
+ <reg32 offset="0x88da" name="RB_BLIT_DST_PITCH" low="0" high="15" shr="6" type="uint"/>
<!-- array-pitch is size of layer -->
- <reg32 offset="0x88db" name="RB_BLIT_DST_ARRAY_PITCH" shr="6" type="uint"/>
- <reg64 offset="0x88dc" name="RB_BLIT_FLAG_DST" type="waddress"/>
+ <reg32 offset="0x88db" name="RB_BLIT_DST_ARRAY_PITCH" low="0" high="28" shr="6" type="uint"/>
+ <reg64 offset="0x88dc" name="RB_BLIT_FLAG_DST" type="waddress" align="64"/>
<reg32 offset="0x88dc" name="RB_BLIT_FLAG_DST_LO"/>
<reg32 offset="0x88dd" name="RB_BLIT_FLAG_DST_HI"/>
<reg32 offset="0x88de" name="RB_BLIT_FLAG_DST_PITCH">
<bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
- <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
+ <bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/>
</reg32>
<reg32 offset="0x88df" name="RB_BLIT_CLEAR_COLOR_DW0"/>
then probably a component mask, I always see 0xf
</doc>
<bitfield name="CLEAR_MASK" low="4" high="7"/>
+ <bitfield name="UNK8" low="8" high="9"/>
+ <bitfield name="UNK12" low="12" high="15"/>
</reg32>
-
+ <!-- 0x88e4-0x88ef invalid -->
<!-- always 0x0 ? -->
- <reg32 offset="0x88f0" name="RB_UNKNOWN_88F0"/>
-
+ <reg32 offset="0x88f0" name="RB_UNKNOWN_88F0" low="0" high="11"/>
+ <!-- could be for separate stencil? (or may not be a flag buffer at all) -->
+ <reg64 offset="0x88f1" name="RB_UNK_FLAG_BUFFER_BASE" type="waddress" align="64"/>
+ <reg32 offset="0x88f3" name="RB_UNK_FLAG_BUFFER_PITCH">
+ <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
+ <bitfield name="ARRAY_PITCH" low="11" high="23" shr="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x88f4" name="RB_UNKNOWN_88F4" low="0" high="2"/>
+ <!-- 0x88f5-0x88ff invalid -->
<reg32 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE_LO"/>
<reg32 offset="0x8901" name="RB_DEPTH_FLAG_BUFFER_BASE_HI"/>
- <reg64 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE" type="waddress"/>
+ <reg64 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE" type="waddress" align="64"/>
<reg32 offset="0x8902" name="RB_DEPTH_FLAG_BUFFER_PITCH">
- <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
- <bitfield name="ARRAY_PITCH" low="11" high="24" shr="7" type="uint"/>
+ <bitfield name="PITCH" low="0" high="6" shr="6" type="uint"/>
+ <!-- TODO: actually part of array pitch -->
+ <bitfield name="UNK8" low="8" high="10"/>
+ <bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/>
</reg32>
<array offset="0x8903" name="RB_MRT_FLAG_BUFFER" stride="3" length="8">
<reg32 offset="0" name="ADDR_LO"/>
<reg32 offset="1" name="ADDR_HI"/>
- <reg64 offset="0" name="ADDR" type="waddress"/>
+ <reg64 offset="0" name="ADDR" type="waddress" align="64"/>
<reg32 offset="2" name="PITCH">
<bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
- <bitfield name="ARRAY_PITCH" low="11" high="24" shr="7" type="uint"/> <!-- ??? -->
+ <bitfield name="ARRAY_PITCH" low="11" high="28" shr="7" type="uint"/>
</reg32>
</array>
+ <!-- 0x891b-0x8926 invalid -->
<reg32 offset="0x8927" name="RB_SAMPLE_COUNT_ADDR_LO"/>
<reg32 offset="0x8928" name="RB_SAMPLE_COUNT_ADDR_HI"/>
+ <reg64 offset="0x8927" name="RB_SAMPLE_COUNT_ADDR" type="waddress" align="16"/>
+ <!-- 0x8929-0x89ff invalid -->
+
+ <!-- TODO: there are some registers in the 0x8a00-0x8bff range -->
<reg32 offset="0x8c00" name="RB_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl"/>
- <reg32 offset="0x8c01" name="RB_UNKNOWN_8C01"/>
+ <reg32 offset="0x8c01" name="RB_2D_UNKNOWN_8C01" low="0" high="31"/>
<bitset name="a6xx_2d_surf_info" inline="yes">
<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
<bitfield name="UNK22" pos="22" type="boolean"/>
</bitset>
+ <!-- 0x8c02-0x8c16 invalid -->
+ <!-- TODO: RB_2D_DST_INFO has 17 valid bits (doesn't match a6xx_2d_surf_info) -->
<reg32 offset="0x8c17" name="RB_2D_DST_INFO" type="a6xx_2d_surf_info"/>
<reg32 offset="0x8c18" name="RB_2D_DST_LO"/>
<reg32 offset="0x8c19" name="RB_2D_DST_HI"/>
- <reg64 offset="0x8c18" name="RB_2D_DST" type="waddress"/>
- <reg32 offset="0x8c1a" name="RB_2D_DST_SIZE">
- <bitfield name="PITCH" low="0" high="15" shr="6" type="uint"/>
- </reg32>
+ <reg64 offset="0x8c18" name="RB_2D_DST" type="waddress" align="64"/>
+ <reg32 offset="0x8c1a" name="RB_2D_DST_PITCH" low="0" high="15" shr="6" type="uint"/>
+ <!-- this is a guess but seems likely (for NV12/IYUV): -->
+ <reg64 offset="0x8c1b" name="RB_2D_DST_PLANE1" type="waddress" align="64"/>
+ <reg32 offset="0x8c1d" name="RB_2D_DST_PLANE_PITCH" low="0" high="15" shr="6" type="uint"/>
+ <reg64 offset="0x8c1e" name="RB_2D_DST_PLANE2" type="waddress" align="64"/>
<reg32 offset="0x8c20" name="RB_2D_DST_FLAGS_LO"/>
<reg32 offset="0x8c21" name="RB_2D_DST_FLAGS_HI"/>
- <reg64 offset="0x8c20" name="RB_2D_DST_FLAGS" type="waddress"/>
- <reg32 offset="0x8c22" name="RB_2D_DST_FLAGS_PITCH">
- <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
- <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
- </reg32>
+ <reg64 offset="0x8c20" name="RB_2D_DST_FLAGS" type="waddress" align="64"/>
+ <reg32 offset="0x8c22" name="RB_2D_DST_FLAGS_PITCH" low="0" high="7" shr="6" type="uint"/>
+ <!-- this is a guess but seems likely (for NV12 with UBWC): -->
+ <reg64 offset="0x8c23" name="RB_2D_DST_FLAGS_PLANE" type="waddress" align="64"/>
+ <reg32 offset="0x8c25" name="RB_2D_DST_FLAGS_PLANE_PITCH" low="0" high="7" shr="6" type="uint"/>
+ <!-- TODO: 0x8c26-0x8c33 are all full 32-bit registers -->
<!-- unlike a5xx, these are per channel values rather than packed -->
<reg32 offset="0x8c2c" name="RB_2D_SRC_SOLID_C0"/>
<reg32 offset="0x8c2d" name="RB_2D_SRC_SOLID_C1"/>
<reg32 offset="0x8c2e" name="RB_2D_SRC_SOLID_C2"/>
<reg32 offset="0x8c2f" name="RB_2D_SRC_SOLID_C3"/>
+ <!-- 0x8c34-0x8dff invalid -->
- <!-- always 0x1 ? -->
+ <!-- always 0x1 ? either doesn't exist for a650 or write-only: -->
<reg32 offset="0x8e01" name="RB_UNKNOWN_8E01"/>
-
- <reg32 offset="0x8e04" name="RB_UNKNOWN_8E04"/>
-
+ <!-- 0x8e00-0x8e03 invalid -->
+ <reg32 offset="0x8e04" name="RB_UNKNOWN_8E04"/> <!-- TODO: valid mask 0xfffffeff -->
+ <reg32 offset="0x8e05" name="RB_ADDR_MODE_CNTL" pos="0" type="boolean"/>
+ <!-- 0x8e06 invalid -->
<reg32 offset="0x8e07" name="RB_CCU_CNTL">
<!-- offset into GMEM for something.
important for sysmem path
a618: 0x7c000 a630/a640: 0xf8000 a650: 0x114000
SYSMEM path values:
a618: 0x10000 a630/a640: 0x20000 a650: 0x30000
+ TODO: valid mask 0xfffffc1f
-->
<bitfield name="OFFSET" low="23" high="31" shr="12" type="hex"/>
<bitfield name="GMEM" pos="22" type="boolean"/> <!-- set for GMEM path -->
<bitfield name="UNK2" pos="2" type="boolean"/> <!-- sometimes set with GMEM? -->
</reg32>
-
- <reg32 offset="0x9100" name="VPC_UNKNOWN_9100"/>
+ <reg32 offset="0x8e08" name="RB_NC_MODE_CNTL">
+ <bitfield name="MODE" pos="0" type="boolean"/>
+ <bitfield name="LOWER_BIT" low="1" high="2" type="uint"/>
+ <bitfield name="MIN_ACCESS_LENGTH" pos="3" type="boolean"/> <!-- true=64b false=32b -->
+ <bitfield name="AMSBC" pos="4" type="boolean"/>
+ <bitfield name="UPPER_BIT" pos="10" type="uint"/>
+ <bitfield name="RGB565_PREDICATOR" pos="11" type="boolean"/>
+ <bitfield name="UNK12" low="12" high="13"/>
+ </reg32>
+ <!-- 0x8e09-0x8e0f invalid -->
+ <reg32 offset="0x8e10" name="RB_PERFCTR_RB_SEL_0"/>
+ <reg32 offset="0x8e11" name="RB_PERFCTR_RB_SEL_1"/>
+ <reg32 offset="0x8e12" name="RB_PERFCTR_RB_SEL_2"/>
+ <reg32 offset="0x8e13" name="RB_PERFCTR_RB_SEL_3"/>
+ <reg32 offset="0x8e14" name="RB_PERFCTR_RB_SEL_4"/>
+ <reg32 offset="0x8e15" name="RB_PERFCTR_RB_SEL_5"/>
+ <reg32 offset="0x8e16" name="RB_PERFCTR_RB_SEL_6"/>
+ <reg32 offset="0x8e17" name="RB_PERFCTR_RB_SEL_7"/>
+ <reg32 offset="0x8e18" name="RB_PERFCTR_CCU_SEL_0"/>
+ <reg32 offset="0x8e19" name="RB_PERFCTR_CCU_SEL_1"/>
+ <reg32 offset="0x8e1a" name="RB_PERFCTR_CCU_SEL_2"/>
+ <reg32 offset="0x8e1b" name="RB_PERFCTR_CCU_SEL_3"/>
+ <reg32 offset="0x8e1c" name="RB_PERFCTR_CCU_SEL_4"/>
+ <!-- 0x8e1d-0x8e1f invalid -->
+ <!-- 0x8e20-0x8e25 more perfcntr sel? -->
+ <!-- 0x8e26-0x8e27 invalid -->
+ <reg32 offset="0x8e28" name="RB_UNKNOWN_8E28" low="0" high="10"/>
+ <!-- 0x8e29-0x8e2b invalid -->
+ <reg32 offset="0x8e2c" name="RB_PERFCTR_CMP_SEL_0"/>
+ <reg32 offset="0x8e2d" name="RB_PERFCTR_CMP_SEL_1"/>
+ <reg32 offset="0x8e2e" name="RB_PERFCTR_CMP_SEL_2"/>
+ <reg32 offset="0x8e2f" name="RB_PERFCTR_CMP_SEL_3"/>
+ <reg32 offset="0x8e3b" name="RB_RB_SUB_BLOCK_SEL_CNTL_HOST"/>
+ <reg32 offset="0x8e3d" name="RB_RB_SUB_BLOCK_SEL_CNTL_CD"/>
+ <!-- 0x8e3e-0x8e4f invalid -->
+ <!-- GMEM save/restore for preemption: -->
+ <reg32 offset="0x8e50" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE" pos="0" type="boolean"/>
+ <!-- address for GMEM save/restore? -->
+ <reg32 offset="0x8e51" name="RB_UNKNOWN_8E51" type="waddress" align="1"/>
+ <!-- 0x8e53-0x8e7f invalid -->
+ <!-- 0x8e80-0x8e83 are valid -->
+ <!-- 0x8e84-0x90ff invalid -->
+
+ <!-- 0x9000-0x90ff invalid -->
+
+ <!-- something to do with geometry shader: -->
+ <reg32 offset="0x9100" name="VPC_UNKNOWN_9100" low="0" high="7"/>
<bitset name="a6xx_vpc_xs_clip_cntl" inline="yes">
<bitfield name="CLIP_MASK" low="0" high="7" type="uint"/>
<bitset name="a6xx_vpc_xs_layer_cntl" inline="yes">
<bitfield name="LAYERLOC" low="0" high="7" type="uint"/>
- <bitfield name="UNKLOC" low="8" high="15" type="uint"/>
+ <bitfield name="VIEWLOC" low="8" high="15" type="uint"/>
</bitset>
<reg32 offset="0x9104" name="VPC_VS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl"/>
<reg32 offset="0x9105" name="VPC_GS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl"/>
<reg32 offset="0x9106" name="VPC_DS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl"/>
- <reg32 offset="0x9107" name="VPC_UNKNOWN_9107"/>
+ <reg32 offset="0x9107" name="VPC_UNKNOWN_9107" pos="2"/>
<reg32 offset="0x9108" name="VPC_POLYGON_MODE">
<bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
</reg32>
-
+ <!-- 0x9109-0x91ff invalid -->
<array offset="0x9200" name="VPC_VARYING_INTERP" stride="1" length="8">
<reg32 offset="0x0" name="MODE"/>
</array>
</array>
<!-- always 0x0 -->
- <reg32 offset="0x9210" name="VPC_UNKNOWN_9210"/>
- <reg32 offset="0x9211" name="VPC_UNKNOWN_9211"/>
+ <reg32 offset="0x9210" name="VPC_UNKNOWN_9210" low="0" high="31"/>
+ <reg32 offset="0x9211" name="VPC_UNKNOWN_9211" low="0" high="31"/>
<array offset="0x9212" name="VPC_VAR" stride="1" length="4">
<!-- one bit per varying component: -->
</array>
<reg32 offset="0x9216" name="VPC_SO_CNTL">
+ <bitfield name="UNK0" low="0" high="7"/>
<!-- always 0x10000 when SO enabled.. -->
<bitfield name="ENABLE" pos="16" type="boolean"/>
</reg32>
+ <!-- special register, write multiple times to load SO program (not readable) -->
<reg32 offset="0x9217" name="VPC_SO_PROG">
<bitfield name="A_BUF" low="0" high="1" type="uint"/>
<bitfield name="A_OFF" low="2" high="10" shr="2" type="uint"/>
<reg32 offset="0x9218" name="VPC_SO_STREAM_COUNTS_LO"/>
<reg32 offset="0x9219" name="VPC_SO_STREAM_COUNTS_HI"/>
+ <reg32 offset="0x9218" name="VPC_SO_STREAM_COUNTS" type="waddress" align="32"/>
<array offset="0x921a" name="VPC_SO" stride="7" length="4">
- <reg64 offset="0" name="BUFFER_BASE" type="waddress"/>
+ <reg64 offset="0" name="BUFFER_BASE" type="waddress" align="32"/>
<reg32 offset="0" name="BUFFER_BASE_LO"/>
<reg32 offset="1" name="BUFFER_BASE_HI"/>
- <reg32 offset="2" name="BUFFER_SIZE"/>
- <reg32 offset="3" name="NCOMP"/> <!-- component count -->
- <reg32 offset="4" name="BUFFER_OFFSET"/>
- <reg64 offset="5" name="FLUSH_BASE" type="waddress"/>
+ <reg32 offset="2" name="BUFFER_SIZE" low="2" high="31" shr="2"/>
+ <reg32 offset="3" name="NCOMP" low="0" high="9"/> <!-- component count -->
+ <reg32 offset="4" name="BUFFER_OFFSET" low="2" high="31" shr="2"/>
+ <reg64 offset="5" name="FLUSH_BASE" type="waddress" align="32"/>
<reg32 offset="5" name="FLUSH_BASE_LO"/>
<reg32 offset="6" name="FLUSH_BASE_HI"/>
</array>
- <!-- always 0x0 ? -->
- <reg32 offset="0x9236" name="VPC_UNKNOWN_9236">
- <bitfield name="POINT_COORD_INVERT" pos="0" type="uint"/>
+ <reg32 offset="0x9236" name="VPC_POINT_COORD_INVERT">
+ <bitfield name="INVERT" pos="0" type="boolean"/>
</reg32>
-
+ <!-- 0x9237-0x92ff invalid -->
<!-- always 0x0 ? -->
- <reg32 offset="0x9300" name="VPC_UNKNOWN_9300"/>
+ <reg32 offset="0x9300" name="VPC_UNKNOWN_9300" low="0" high="2"/>
<bitset name="a6xx_vpc_xs_pack" inline="yes">
<doc>
<bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
<bitfield name="POSITIONLOC" low="8" high="15" type="uint"/>
<bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
+ <bitfield name="UNK24" low="24" high="27"/>
</bitset>
<reg32 offset="0x9301" name="VPC_VS_PACK" type="a6xx_vpc_xs_pack"/>
<reg32 offset="0x9302" name="VPC_GS_PACK" type="a6xx_vpc_xs_pack"/>
</reg32>
<reg32 offset="0x9305" name="VPC_SO_BUF_CNTL">
+ <!-- TODO: the first 12 bits are valid, likely 3-bit enum instead of bools -->
<bitfield name="BUF0" pos="0" type="boolean"/>
<bitfield name="BUF1" pos="3" type="boolean"/>
<bitfield name="BUF2" pos="6" type="boolean"/>
<bitfield name="BUF3" pos="9" type="boolean"/>
<bitfield name="ENABLE" pos="15" type="boolean"/>
+ <bitfield name="UNK16" low="16" high="19"/>
</reg32>
- <reg32 offset="0x9306" name="VPC_SO_OVERRIDE">
- <bitfield name="SO_DISABLE" pos="0" type="boolean"/>
+ <reg32 offset="0x9306" name="VPC_SO_DISABLE">
+ <bitfield name="DISABLE" pos="0" type="boolean"/>
</reg32>
+ <!-- 0x9307-0x95ff invalid -->
- <!-- always 0x0 ? -->
- <reg32 offset="0x9600" name="VPC_UNKNOWN_9600"/>
- <!-- always 0x0 ? -->
- <reg32 offset="0x9602" name="VPC_UNKNOWN_9602"/>
+ <!-- TODO: 0x9600-0x97ff range -->
+ <reg32 offset="0x9600" name="VPC_UNKNOWN_9600"/> <!-- always 0x0 ? TODO: 0x1fbf37ff valid mask -->
+ <reg32 offset="0x9601" name="VPC_ADDR_MODE_CNTL" pos="0" type="boolean"/>
+ <reg32 offset="0x9602" name="VPC_UNKNOWN_9602" pos="0"/> <!-- always 0x0 ? -->
+ <reg32 offset="0x9603" name="VPC_UNKNOWN_9603" low="0" high="26"/>
+ <reg32 offset="0x9604" name="VPC_PERFCTR_VPC_SEL_0"/>
+ <reg32 offset="0x9605" name="VPC_PERFCTR_VPC_SEL_1"/>
+ <reg32 offset="0x9606" name="VPC_PERFCTR_VPC_SEL_2"/>
+ <reg32 offset="0x9607" name="VPC_PERFCTR_VPC_SEL_3"/>
+ <reg32 offset="0x9608" name="VPC_PERFCTR_VPC_SEL_4"/>
+ <reg32 offset="0x9609" name="VPC_PERFCTR_VPC_SEL_5"/>
+ <!-- 0x960a-0x9623 invalid -->
+ <!-- TODO: regs from 0x9624-0x963a -->
+ <!-- 0x963b-0x97ff invalid -->
- <reg32 offset="0x9800" name="PC_TESS_NUM_VERTEX"/>
+ <reg32 offset="0x9800" name="PC_TESS_NUM_VERTEX" low="0" high="5" type="uint"/>
<!-- always 0x0 ? -->
- <reg32 offset="0x9801" name="PC_UNKNOWN_9801"/>
+ <reg32 offset="0x9801" name="PC_UNKNOWN_9801">
+ <bitfield name="UNK0" low="0" high="10"/>
+ <bitfield name="UNK13" pos="13"/>
+ </reg32>
<enum name="a6xx_tess_spacing">
- <value value="0x0" name="TESS_EQUAL"/>
- <value value="0x2" name="TESS_FRACTIONAL_ODD"/>
- <value value="0x3" name="TESS_FRACTIONAL_EVEN"/>
+ <value value="0x0" name="TESS_EQUAL"/>
+ <value value="0x2" name="TESS_FRACTIONAL_ODD"/>
+ <value value="0x3" name="TESS_FRACTIONAL_EVEN"/>
</enum>
-
<enum name="a6xx_tess_output">
- <value value="0x0" name="TESS_POINTS"/>
- <value value="0x1" name="TESS_LINES"/>
- <value value="0x2" name="TESS_CW_TRIS"/>
- <value value="0x3" name="TESS_CCW_TRIS"/>
+ <value value="0x0" name="TESS_POINTS"/>
+ <value value="0x1" name="TESS_LINES"/>
+ <value value="0x2" name="TESS_CW_TRIS"/>
+ <value value="0x3" name="TESS_CCW_TRIS"/>
</enum>
-
<reg32 offset="0x9802" name="PC_TESS_CNTL">
- <bitfield name="SPACING" low="0" high="1" type="a6xx_tess_spacing"/>
- <bitfield name="OUTPUT" low="2" high="3" type="a6xx_tess_output"/>
+ <bitfield name="SPACING" low="0" high="1" type="a6xx_tess_spacing"/>
+ <bitfield name="OUTPUT" low="2" high="3" type="a6xx_tess_output"/>
</reg32>
- <!-- probably: -->
- <reg32 offset="0x9803" name="PC_RESTART_INDEX"/>
- <reg32 offset="0x9804" name="PC_MODE_CNTL"/>
+ <reg32 offset="0x9803" name="PC_RESTART_INDEX" low="0" high="31" type="uint"/>
+ <reg32 offset="0x9804" name="PC_MODE_CNTL" low="0" high="7"/>
<!-- always 0x1 ? -->
- <reg32 offset="0x9805" name="PC_UNKNOWN_9805"/>
+ <reg32 offset="0x9805" name="PC_UNKNOWN_9805" low="0" high="2"/>
<!-- probably a mirror of VFD_CONTROL_6 -->
- <reg32 offset="0x9806" name="PC_PRIMID_CNTL">
- <bitfield name="PRIMID_PASSTHRU" pos="0" type="boolean"/>
- </reg32>
+ <reg32 offset="0x9806" name="PC_PRIMID_PASSTHRU" pos="0" type="boolean"/>
+ <!-- 0x980b-0x983f invalid -->
+ <!-- 0x9840 - 0x9842 are not readable -->
<reg32 offset="0x9840" name="PC_DRAW_CMD">
<bitfield name="STATE_ID" low="0" high="7"/>
</reg32>
<bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
</reg32>
- <reg32 offset="0x9980" name="PC_UNKNOWN_9980"/>
+ <!-- 0x9843-0x997f invalid -->
<reg32 offset="0x9981" name="PC_POLYGON_MODE">
<bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
</reg32>
+ <reg32 offset="0x9980" name="PC_UNKNOWN_9980" low="0" high="2"/>
- <reg32 offset="0x9990" name="PC_UNKNOWN_9990"/>
+ <!-- 0x9982-0x9aff invalid -->
<reg32 offset="0x9b00" name="PC_PRIMITIVE_CNTL_0">
<bitfield name="PRIMITIVE_RESTART" pos="0" type="boolean"/>
<!-- maybe? b1 seems always set, so just assume it is for now: -->
<bitfield name="PROVOKING_VTX_LAST" pos="1" type="boolean"/>
<bitfield name="TESS_UPPER_LEFT_DOMAIN_ORIGIN" pos="2" type="boolean"/>
+ <bitfield name="UNK3" pos="3" type="boolean"/>
</reg32>
<bitset name="a6xx_xs_out_cntl" inline="yes">
</doc>
<bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
<bitfield name="PSIZE" pos="8" type="boolean"/>
- <!-- layer / primitiveid only for GS (apparently) -->
<bitfield name="LAYER" pos="9" type="boolean"/>
+ <bitfield name="VIEW" pos="10" type="boolean"/>
+ <!-- note: PC_VS_OUT_CNTL doesn't have the PRIMITIVE_ID bit -->
<bitfield name="PRIMITIVE_ID" pos="11" type="boolean"/>
<bitfield name="CLIP_MASK" low="16" high="23" type="uint"/>
</bitset>
<reg32 offset="0x9b01" name="PC_VS_OUT_CNTL" type="a6xx_xs_out_cntl"/>
<reg32 offset="0x9b02" name="PC_GS_OUT_CNTL" type="a6xx_xs_out_cntl"/>
- <reg32 offset="0x9b03" name="PC_PRIMITIVE_CNTL_3"/>
+ <reg32 offset="0x9b03" name="PC_PRIMITIVE_CNTL_3" pos="11"/>
<reg32 offset="0x9b04" name="PC_DS_OUT_CNTL" type="a6xx_xs_out_cntl"/>
<reg32 offset="0x9b05" name="PC_PRIMITIVE_CNTL_5">
<doc>
geometry shader
</doc>
+ <!-- TODO: first 16 bits are valid so something is wrong or missing here -->
<bitfield name="GS_VERTICES_OUT" low="0" high="7" type="uint"/>
<bitfield name="GS_INVOCATIONS" low="10" high="14" type="uint"/>
<bitfield name="GS_OUTPUT" low="16" high="17" type="a6xx_tess_output"/>
+ <bitfield name="UNK18" pos="18"/>
</reg32>
<reg32 offset="0x9b06" name="PC_PRIMITIVE_CNTL_6">
<doc>
- size in vec4s of per-primitive storage for gs
+ size in vec4s of per-primitive storage for gs. TODO: not actually in VPC
</doc>
- <bitfield name="STRIDE_IN_VPC" low="0" high="8" type="uint"/>
+ <bitfield name="STRIDE_IN_VPC" low="0" high="10" type="uint"/>
</reg32>
+ <!-- something gs related: -->
+ <reg32 offset="0x9b07" name="PC_UNKNOWN_9B07" low="0" high="6"/>
- <reg32 offset="0x9b07" name="PC_UNKNOWN_9B07"/>
-
+ <reg32 offset="0x9b08" name="PC_UNKNOWN_9B08" low="0" high="15"/>
+ <!-- 0x9b09-0x9bff invalid -->
+ <reg32 offset="0x9c00" name="PC_2D_EVENT_CMD">
+ <!-- special register (but note first 8 bits can be written/read) -->
+ <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
+ <bitfield name="STATE_ID" low="8" high="15"/>
+ </reg32>
+ <!-- 0x9c01-0x9dff invalid -->
+ <!-- TODO: 0x9e00-0xa000 range incomplete -->
+ <reg32 offset="0x9e00" name="PC_DBG_ECO_CNTL"/>
+ <reg32 offset="0x9e01" name="PC_ADDR_MODE_CNTL"/>
<reg32 offset="0x9e08" name="PC_TESSFACTOR_ADDR_LO"/>
<reg32 offset="0x9e09" name="PC_TESSFACTOR_ADDR_HI"/>
+ <reg32 offset="0x9e08" name="PC_TESSFACTOR_ADDR" type="waddress" align="32"/>
<!-- These match the contents of CP_SET_BIN_DATA (not written directly) -->
<reg32 offset="0x9e11" name="PC_VSTREAM_CONTROL">
+ <bitfield name="UNK0" low="0" high="15"/>
<bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
<bitfield name="VSC_N" low="22" high="26" type="uint"/>
</reg32>
- <reg32 offset="0x9e12" name="PC_BIN_DATA_ADDR2_LO"/>
- <reg32 offset="0x9e13" name="PC_BIN_DATA_ADDR2_HI"/>
- <reg32 offset="0x9e14" name="PC_BIN_DATA_ADDR_LO"/>
- <reg32 offset="0x9e15" name="PC_BIN_DATA_ADDR_HI"/>
+ <reg32 offset="0x9e12" name="PC_BIN_DATA_ADDR2" type="waddress" align="32"/>
+ <reg32 offset="0x9e14" name="PC_BIN_DATA_ADDR" type="waddress" align="32"/>
- <reg32 offset="0x9c00" name="PC_2D_EVENT_CMD">
- <bitfield name="STATE_ID" low="8" high="15"/>
- <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
- </reg32>
+ <reg32 offset="0x9e34" name="PC_PERFCTR_PC_SEL_0"/>
+ <reg32 offset="0x9e35" name="PC_PERFCTR_PC_SEL_1"/>
+ <reg32 offset="0x9e36" name="PC_PERFCTR_PC_SEL_2"/>
+ <reg32 offset="0x9e37" name="PC_PERFCTR_PC_SEL_3"/>
+ <reg32 offset="0x9e38" name="PC_PERFCTR_PC_SEL_4"/>
+ <reg32 offset="0x9e39" name="PC_PERFCTR_PC_SEL_5"/>
+ <reg32 offset="0x9e3a" name="PC_PERFCTR_PC_SEL_6"/>
+ <reg32 offset="0x9e3b" name="PC_PERFCTR_PC_SEL_7"/>
<!-- always 0x0 -->
<reg32 offset="0x9e72" name="PC_UNKNOWN_9E72"/>
<bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>
<bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/>
<bitfield name="SAMPMASK_REGID" low="16" high="23" type="a3xx_regid"/>
+ <bitfield name="STENCILREF_REGID" low="24" high="31" type="a3xx_regid"/>
</reg32>
<reg32 offset="0xa98d" name="SP_FS_OUTPUT_CNTL1">
<bitfield name="MRT" low="0" high="3" type="uint"/>
projects / mesa.git / blobdiff