<bitfield high="1" low="1" name="CP_AHB_BUSY_CP_MASTER" />
<bitfield high="0" low="0" name="CP_AHB_BUSY_CX_MASTER"/>
</reg32>
- <reg32 offset="0x0213" name="RBBM_STATUS3"/>
+ <reg32 offset="0x0213" name="RBBM_STATUS3">
+ <bitfield pos="24" name="SMMU_STALLED_ON_FAULT" type="boolean"/>
+ </reg32>
<reg32 offset="0x0215" name="RBBM_VBIF_GX_RESET_STATUS"/>
<reg32 offset="0x0400" name="RBBM_PERFCTR_CP_0_LO"/>
<reg32 offset="0x0401" name="RBBM_PERFCTR_CP_0_HI"/>
<!-- always 0x03200000 ? -->
<reg32 offset="0x0e12" name="UCHE_UNKNOWN_0E12"/>
- <reg32 offset="0x8000" name="GRAS_DISABLE_CNTL">
- <!-- likely something clip-disable related -->
- <bitfield name="UNK0" pos="0" type="boolean"/>
+ <reg32 offset="0x8000" name="GRAS_CL_CNTL">
+ <bitfield name="CLIP_DISABLE" pos="0" type="boolean"/>
+ <bitfield name="ZNEAR_CLIP_DISABLE" pos="1" type="boolean"/>
+ <bitfield name="ZFAR_CLIP_DISABLE" pos="2" type="boolean"/>
+ <!-- set with depthClampEnable, not clear what it does -->
+ <bitfield name="UNK5" pos="5" type="boolean"/>
+ <!-- controls near z clip behavior (set for vulkan) -->
+ <bitfield name="ZERO_GB_SCALE_Z" pos="6" type="boolean"/>
<!-- guess based on a3xx and meaning of bits 8 and 9
if the guess is right then this is related to point sprite clipping -->
<bitfield name="VP_CLIP_CODE_IGNORE" pos="7" type="boolean"/>
<value value="0x3" name="LAYER_2D_ARRAY"/>
</enum>
- <reg32 offset="0x8004" name="GRAS_LAYER_CNTL">
- <bitfield name="LAYERED" pos="0" type="boolean"/>
- <bitfield name="TYPE" low="1" high="2" type="a6xx_layer_type"/>
- </reg32>
+ <!-- index of highest layer that can be written to via gl_Layer -->
+ <reg32 offset="0x8004" name="GRAS_MAX_LAYER_INDEX" type="uint"/>
<reg32 offset="0x8005" name="GRAS_CNTL">
<!-- see also RB_RENDER_CONTROL0 -->
<reg32 offset="0x8014" name="GRAS_CL_VPORT_ZOFFSET_0" type="float"/>
<reg32 offset="0x8015" name="GRAS_CL_VPORT_ZSCALE_0" type="float"/>
+ <!-- not clear what it does, mirrors RB_Z_CLAMP_MIN -->
+ <reg32 offset="0x8070" name="GRAS_CL_Z_CLAMP_MIN" type="float"/>
+ <reg32 offset="0x8071" name="GRAS_CL_Z_CLAMP_MAX" type="float"/>
+
<reg32 offset="0x8090" name="GRAS_SU_CNTL">
<bitfield name="CULL_FRONT" pos="0" type="boolean"/>
<bitfield name="CULL_BACK" pos="1" type="boolean"/>
<bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
</reg32>
- <!-- always 0x0 -->
- <reg32 offset="0x80a4" name="GRAS_UNKNOWN_80A4"/>
- <!-- always 0x0 -->
- <reg32 offset="0x80a5" name="GRAS_UNKNOWN_80A5"/>
- <!-- always 0x0 -->
- <reg32 offset="0x80a6" name="GRAS_UNKNOWN_80A6"/>
+ <bitset name="a6xx_sample_config" inline="yes">
+ <bitfield name="LOCATION_ENABLE" pos="1" type="boolean"/>
+ </bitset>
+
+ <bitset name="a6xx_sample_locations" inline="yes">
+ <bitfield name="SAMPLE_0_X" low="0" high="3" radix="4" type="fixed"/>
+ <bitfield name="SAMPLE_0_Y" low="4" high="7" radix="4" type="fixed"/>
+ <bitfield name="SAMPLE_1_X" low="8" high="11" radix="4" type="fixed"/>
+ <bitfield name="SAMPLE_1_Y" low="12" high="15" radix="4" type="fixed"/>
+ <bitfield name="SAMPLE_2_X" low="16" high="19" radix="4" type="fixed"/>
+ <bitfield name="SAMPLE_2_Y" low="20" high="23" radix="4" type="fixed"/>
+ <bitfield name="SAMPLE_3_X" low="24" high="27" radix="4" type="fixed"/>
+ <bitfield name="SAMPLE_3_Y" low="28" high="31" radix="4" type="fixed"/>
+ </bitset>
+
+ <reg32 offset="0x80a4" name="GRAS_SAMPLE_CONFIG" type="a6xx_sample_config"/>
+ <reg32 offset="0x80a5" name="GRAS_SAMPLE_LOCATION_0" type="a6xx_sample_locations"/>
+ <reg32 offset="0x80a6" name="GRAS_SAMPLE_LOCATION_1" type="a6xx_sample_locations"/>
+
<!-- always 0x0 -->
<reg32 offset="0x80af" name="GRAS_UNKNOWN_80AF"/>
<bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
</reg32>
- <!-- always 0x0 ? -->
- <reg32 offset="0x8804" name="RB_UNKNOWN_8804"/>
- <!-- always 0x0 ? -->
- <reg32 offset="0x8805" name="RB_UNKNOWN_8805"/>
- <!-- always 0x0 ? -->
- <reg32 offset="0x8806" name="RB_UNKNOWN_8806"/>
+ <reg32 offset="0x8804" name="RB_SAMPLE_CONFIG" type="a6xx_sample_config"/>
+ <reg32 offset="0x8805" name="RB_SAMPLE_LOCATION_0" type="a6xx_sample_locations"/>
+ <reg32 offset="0x8806" name="RB_SAMPLE_LOCATION_1" type="a6xx_sample_locations"/>
<!--
note: maybe not actually called RB_RENDER_CONTROLn (since RB_RENDER_CNTL
<bitfield name="Z_ENABLE" pos="0" type="boolean"/>
<bitfield name="Z_WRITE_ENABLE" pos="1" type="boolean"/>
<bitfield name="ZFUNC" low="2" high="4" type="adreno_compare_func"/>
+ <bitfield name="Z_CLAMP_ENABLE" pos="5" type="boolean"/>
<doc>Z_TEST_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER</doc>
<bitfield name="Z_TEST_ENABLE" pos="6" type="boolean"/>
</reg32>
<bitfield name="ENABLE" pos="0" type="boolean"/>
</reg32>
+ <!-- clamps depth value for depth test/write -->
+ <reg32 offset="0x88c0" name="RB_Z_CLAMP_MIN" type="float"/>
+ <reg32 offset="0x88c1" name="RB_Z_CLAMP_MAX" type="float"/>
+
<reg32 offset="0x88d0" name="RB_UNKNOWN_88D0"/>
<reg32 offset="0x88d1" name="RB_BLIT_SCISSOR_TL" type="adreno_reg_xy"/>
<reg32 offset="0x88d2" name="RB_BLIT_SCISSOR_BR" type="adreno_reg_xy"/>
<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
<bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
<bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
- <!-- b12 seems to be set when UBWC "FLAGS" buffer enabled -->
<bitfield name="FLAGS" pos="12" type="boolean"/>
<bitfield name="SRGB" pos="13" type="boolean"/>
<!-- the rest is only for src -->
<bitfield name="SAMPLES" low="14" high="15" type="a3xx_msaa_samples"/>
<bitfield name="FILTER" pos="16" type="boolean"/>
<bitfield name="SAMPLES_AVERAGE" pos="18" type="boolean"/>
+ <bitfield name="UNK20" pos="20" type="boolean"/>
+ <bitfield name="UNK22" pos="22" type="boolean"/>
</bitset>
<reg32 offset="0x8c17" name="RB_2D_DST_INFO" type="a6xx_2d_surf_info"/>
<reg32 offset="0x8c18" name="RB_2D_DST_LO"/>
<reg32 offset="0x8c19" name="RB_2D_DST_HI"/>
+ <reg64 offset="0x8c18" name="RB_2D_DST" type="waddress"/>
<reg32 offset="0x8c1a" name="RB_2D_DST_SIZE">
<bitfield name="PITCH" low="0" high="15" shr="6" type="uint"/>
</reg32>
<reg32 offset="0x8c20" name="RB_2D_DST_FLAGS_LO"/>
<reg32 offset="0x8c21" name="RB_2D_DST_FLAGS_HI"/>
+ <reg64 offset="0x8c20" name="RB_2D_DST_FLAGS" type="waddress"/>
<reg32 offset="0x8c22" name="RB_2D_DST_FLAGS_PITCH">
<bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
<bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
<reg32 offset="0x8e04" name="RB_UNKNOWN_8E04"/>
- <reg32 offset="0x8e07" name="RB_CCU_CNTL"/> <!-- always 7c400004 or 10000000 -->
+ <reg32 offset="0x8e07" name="RB_CCU_CNTL">
+ <!-- offset into GMEM for something.
+ important for sysmem path
+ BLIT_OP_SCALE also writes to GMEM at this offset for GMEM store
+ blob values for GMEM path (note: close to GMEM size):
+ a618: 0x7c000 a630/a640: 0xf8000 a650: 0x114000
+ SYSMEM path values:
+ a618: 0x10000 a630/a640: 0x20000 a650: 0x30000
+ -->
+ <bitfield name="OFFSET" low="23" high="31" shr="12" type="uint"/>
+ <bitfield name="GMEM" pos="22" type="boolean"/> <!-- set for GMEM path -->
+ <bitfield name="UNK2" pos="2" type="boolean"/> <!-- sometimes set with GMEM? -->
+ </reg32>
<reg32 offset="0x9100" name="VPC_UNKNOWN_9100"/>
plus # of transform-feedback (streamout) varyings if using the
hw streamout (rather than stg instructions in shader)
</doc>
- <bitfield name="STRIDE_IN_VPC" low="0" high="6" type="uint"/>
+ <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
<bitfield name="PSIZE" pos="8" type="boolean"/>
</reg32>
<doc>
geometry shader
</doc>
- <bitfield name="STRIDE_IN_VPC" low="0" high="6" type="uint"/>
+ <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
<bitfield name="PSIZE" pos="8" type="boolean"/>
<bitfield name="LAYER" pos="9" type="boolean"/>
<bitfield name="PRIMITIVE_ID" pos="11" type="boolean"/>
plus # of transform-feedback (streamout) varyings if using the
hw streamout (rather than stg instructions in shader)
</doc>
- <bitfield name="STRIDE_IN_VPC" low="0" high="6" type="uint"/>
+ <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
<bitfield name="PSIZE" pos="8" type="boolean"/>
</reg32>
<reg32 offset="0x9b04" name="PC_PRIMITIVE_CNTL_4">
plus # of transform-feedback (streamout) varyings if using the
hw streamout (rather than stg instructions in shader)
</doc>
- <bitfield name="STRIDE_IN_VPC" low="0" high="6" type="uint"/>
+ <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
<bitfield name="PSIZE" pos="8" type="boolean"/>
</reg32>
<reg32 offset="0x9e72" name="PC_UNKNOWN_9E72"/>
<reg32 offset="0xa000" name="VFD_CONTROL_0">
- <bitfield name="VTXCNT" low="0" high="5" type="uint"/>
+ <bitfield name="FETCH_CNT" low="0" high="5" type="uint"/>
+ <bitfield name="DECODE_CNT" low="8" high="13" type="uint"/>
</reg32>
<reg32 offset="0xa001" name="VFD_CONTROL_1">
<bitfield name="REGID4VTX" low="0" high="7" type="a3xx_regid"/>
</array>
<array offset="0xa090" name="VFD_DECODE" stride="2" length="32">
<reg32 offset="0x0" name="INSTR">
- <!-- IDX appears to index into VFD_FETCH[] -->
+ <!-- IDX and byte OFFSET into VFD_FETCH -->
<bitfield name="IDX" low="0" high="4" type="uint"/>
+ <bitfield name="OFFSET" low="5" high="16"/>
<bitfield name="INSTANCED" pos="17" type="boolean"/>
<bitfield name="FORMAT" low="20" high="27" type="a6xx_format"/>
<bitfield name="SWAP" low="28" high="29" type="a3xx_color_swap"/>
</bitset>
<bitset name="a6xx_sp_xs_config" inline="yes">
+ <!--
+ Each of these are set if the given resource type is used
+ with the Vulkan/bindless binding model.
+ -->
+ <bitfield name="BINDLESS_TEX" pos="0" type="boolean"/>
+ <bitfield name="BINDLESS_SAMP" pos="1" type="boolean"/>
+ <bitfield name="BINDLESS_IBO" pos="2" type="boolean"/>
+ <bitfield name="BINDLESS_UBO" pos="3" type="boolean"/>
+
<bitfield name="ENABLED" pos="8" type="boolean"/>
<!--
number of textures and samplers.. these might be swapped, with GL I
<reg32 offset="0xa800" name="SP_VS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
<reg32 offset="0xa802" name="SP_PRIMITIVE_CNTL">
<!-- # of VS outputs including pos/psize -->
- <bitfield name="VSOUT" low="0" high="4" type="uint"/>
+ <bitfield name="VSOUT" low="0" high="5" type="uint"/>
</reg32>
<array offset="0xa803" name="SP_VS_OUT" stride="1" length="16">
<reg32 offset="0x0" name="REG">
<reg32 offset="0xa873" name="SP_PRIMITIVE_CNTL_GS">
<!-- # of VS outputs including pos/psize -->
- <bitfield name="GSOUT" low="0" high="4" type="uint"/>
+ <bitfield name="GSOUT" low="0" high="5" type="uint"/>
<bitfield name="FLAGS_REGID" low="6" high="13" type="a3xx_regid"/>
</reg32>
<!--
CMD seems always 0x4?? 3d, textureProj, textureLod seem to
skip pre-fetch.. TODO test texelFetch
+ CMD is 0x6 when the Vulkan mode is enabled, and
+ TEX_ID/SAMP_ID refer to the descriptor sets while the
+ indices come from SP_FS_BINDLESS_PREFETCH[n]
-->
<bitfield name="CMD" low="27" high="31"/>
</reg32>
</array>
+ <!-- TODO confirm that this is actually an array -->
+ <array offset="0xa9a3" name="SP_FS_BINDLESS_PREFETCH" stride="1" length="4">
+ <reg32 offset="0" name="CMD">
+ <bitfield name="SAMP_ID" low="0" high="7" type="uint"/>
+ <bitfield name="TEX_ID" low="16" high="23" type="uint"/>
+ </reg32>
+ </array>
+
<reg32 offset="0xa9a7" name="SP_FS_TEX_COUNT" type="uint"/>
<!-- always 0x0 ? -->
<reg32 offset="0xa9e6" name="SP_CS_TEX_CONST_LO"/>
<reg32 offset="0xa9e7" name="SP_CS_TEX_CONST_HI"/>
+ <array offset="0xa9e8" name="SP_CS_BINDLESS_BASE" stride="2" length="5">
+ <reg64 offset="0" name="ADDR" type="waddress"/>
+ </array>
+
<array offset="0xa98e" name="SP_FS_OUTPUT" stride="1" length="8">
<doc>per MRT</doc>
<reg32 offset="0x0" name="REG">
<reg32 offset="0xab04" name="SP_FS_CONFIG" type="a6xx_sp_xs_config"/>
<reg32 offset="0xab05" name="SP_FS_INSTRLEN" type="uint"/>
+ <array offset="0xab10" name="SP_BINDLESS_BASE" stride="2" length="5">
+ <reg64 offset="0" name="ADDR" type="waddress"/>
+ </array>
+
<!--
Combined IBO state for 3d pipe, used for Image and SSBO write/atomic
instructions VS/HS/DS/GS/FS. See SP_CS_IBO_* for compute shaders.
<!-- always 0x3f ? -->
<reg32 offset="0xae0f" name="SP_UNKNOWN_AE0F"/>
+ <!--
+ The downstream kernel calls the debug cluster of registers
+ "a6xx_sp_ps_tp_cluster" but this actually specifies the border
+ color base for compute shaders.
+ -->
+ <reg64 offset="0xb180" name="SP_PS_TP_BORDER_COLOR_BASE_ADDR" type="address"/>
<!-- always 0x0 ? -->
<reg32 offset="0xb182" name="SP_UNKNOWN_B182"/>
<reg32 offset="0xb183" name="SP_UNKNOWN_B183"/>
<reg64 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR" type="address"/>
<reg32 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR_LO"/>
<reg32 offset="0xb303" name="SP_TP_BORDER_COLOR_BASE_ADDR_HI"/>
- <!-- always 0x0 ? -->
- <reg32 offset="0xb304" name="SP_TP_UNKNOWN_B304"/>
+ <reg32 offset="0xb304" name="SP_TP_SAMPLE_CONFIG" type="a6xx_sample_config"/>
+ <reg32 offset="0xb305" name="SP_TP_SAMPLE_LOCATION_0" type="a6xx_sample_locations"/>
+ <reg32 offset="0xb306" name="SP_TP_SAMPLE_LOCATION_1" type="a6xx_sample_locations"/>
<reg32 offset="0xb309" name="SP_TP_UNKNOWN_B309"/>
</reg32>
<reg32 offset="0xb4c2" name="SP_PS_2D_SRC_LO"/>
<reg32 offset="0xb4c3" name="SP_PS_2D_SRC_HI"/>
+ <reg64 offset="0xb4c2" name="SP_PS_2D_SRC" type="waddress"/>
<reg32 offset="0xb4c4" name="SP_PS_2D_SRC_PITCH">
<bitfield name="PITCH" low="9" high="24" shr="6" type="uint"/>
</reg32>
<reg32 offset="0xb4ca" name="SP_PS_2D_SRC_FLAGS_LO"/>
<reg32 offset="0xb4cb" name="SP_PS_2D_SRC_FLAGS_HI"/>
+ <reg64 offset="0xb4ca" name="SP_PS_2D_SRC_FLAGS" type="waddress"/>
<reg32 offset="0xb4cc" name="SP_PS_2D_SRC_FLAGS_PITCH">
<bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
<bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
<reg32 offset="0xb99a" name="HLSQ_CS_KERNEL_GROUP_Y"/>
<reg32 offset="0xb99b" name="HLSQ_CS_KERNEL_GROUP_Z"/>
+ <!-- mirror of SP_CS_BINDLESS_BASE -->
+ <array offset="0xb9c0" name="HLSQ_CS_BINDLESS_BASE" stride="2" length="5">
+ <reg64 offset="0" name="ADDR" type="waddress"/>
+ </array>
+
<!-- probably: -->
<reg32 offset="0xbb08" name="HLSQ_UPDATE_CNTL"/>
<!-- always 0x0 ? -->
<reg32 offset="0xbb11" name="HLSQ_UNKNOWN_BB11"/>
+ <!-- mirror of SP_BINDLESS_BASE -->
+ <array offset="0xbb20" name="HLSQ_BINDLESS_BASE" stride="2" length="5">
+ <reg64 offset="0" name="ADDR" type="waddress"/>
+ </array>
+
<!-- always 0x80 ? -->
<reg32 offset="0xbe00" name="HLSQ_UNKNOWN_BE00"/>
<!-- always 0x0 ? -->
<value name="A6XX_TEX_NEAREST" value="0"/>
<value name="A6XX_TEX_LINEAR" value="1"/>
<value name="A6XX_TEX_ANISO" value="2"/>
+ <value name="A6XX_TEX_CUBIC" value="3"/> <!-- a650 only -->
</enum>
<enum name="a6xx_tex_clamp"> <!-- same as a4xx? -->
<value name="A6XX_TEX_REPEAT" value="0"/>
<value name="A6XX_TEX_ANISO_8" value="3"/>
<value name="A6XX_TEX_ANISO_16" value="4"/>
</enum>
+ <enum name="a6xx_reduction_mode">
+ <value name="A6XX_REDUCTION_MODE_AVERAGE" value="0"/>
+ <value name="A6XX_REDUCTION_MODE_MIN" value="1"/>
+ <value name="A6XX_REDUCTION_MODE_MAX" value="2"/>
+ </enum>
+
<reg32 offset="0" name="0">
<bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/>
<bitfield name="XY_MAG" low="1" high="2" type="a6xx_tex_filter"/>
<bitfield name="MIN_LOD" low="20" high="31" type="ufixed" radix="8"/>
</reg32>
<reg32 offset="2" name="2">
- <bitfield name="BCOLOR_OFFSET" low="0" high="31"/>
+ <bitfield name="REDUCTION_MODE" low="0" high="1" type="a6xx_reduction_mode"/>
+ <bitfield name="BCOLOR_OFFSET" low="7" high="31" shr="7"/>
</reg32>
<reg32 offset="3" name="3"/>
</domain>
</reg32>
<reg32 offset="1" name="1">
<bitfield name="BASE_HI" low="0" high="16"/>
- <!-- size probably in high bits -->
+ <bitfield name="SIZE" low="17" high="31"/> <!-- size in vec4 (4xDWORD) units -->
</reg32>
</domain>
projects / mesa.git / blobdiff