git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
-- /work/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-10 14:59:32)
-- /work/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-10 14:59:32)
-- /work/envytools/rnndb/adreno/a2xx.xml ( 79608 bytes, from 2019-02-11 18:07:21)
-- /work/envytools/rnndb/adreno/adreno_common.xml ( 14239 bytes, from 2018-12-17 18:59:13)
-- /work/envytools/rnndb/adreno/adreno_pm4.xml ( 43155 bytes, from 2019-02-12 18:24:48)
-- /work/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-10 14:59:32)
-- /work/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-10 14:59:32)
-- /work/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-09-28 22:41:49)
-- /work/envytools/rnndb/adreno/a6xx.xml ( 145669 bytes, from 2019-02-15 07:12:43)
-- /work/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-28 22:41:49)
-- /work/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-10 14:59:32)
+- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
+- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
+- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 79608 bytes, from 2019-01-21 14:36:17)
+- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14239 bytes, from 2018-12-05 15:25:53)
+- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43561 bytes, from 2019-06-10 13:39:33)
+- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84030 bytes, from 2019-07-01 13:05:23)
+- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
+- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147548 bytes, from 2019-06-10 13:39:33)
+- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 152605 bytes, from 2019-07-01 13:13:03)
+- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
+- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
Copyright (C) 2013-2019 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
RB6_R32G32B32A32_FLOAT = 130,
RB6_R32G32B32A32_UINT = 131,
RB6_R32G32B32A32_SINT = 132,
+ RB6_Z24_UNORM_S8_UINT = 145,
RB6_X8Z24_UNORM = 160,
};
TFMT6_32_32_32_32_FLOAT = 130,
TFMT6_32_32_32_32_UINT = 131,
TFMT6_32_32_32_32_SINT = 132,
+ TFMT6_Z24_UNORM_S8_UINT = 145,
TFMT6_X8Z24_UNORM = 160,
TFMT6_ETC2_RG11_UNORM = 171,
TFMT6_ETC2_RG11_SNORM = 172,
R2D_FLOAT16 = 3,
};
+enum a6xx_tess_spacing {
+ TESS_EQUAL = 0,
+ TESS_FRACTIONAL_ODD = 2,
+ TESS_FRACTIONAL_EVEN = 3,
+};
+
enum a6xx_tex_filter {
A6XX_TEX_NEAREST = 0,
A6XX_TEX_LINEAR = 1,
#define REG_A6XX_RBBM_PERFCTR_TSE_2_LO 0x0000046a
-#define REG_A6XX_RBBM_PERFCTR_CCU_4_HI 0x00000465
-
-#define REG_A6XX_RBBM_PERFCTR_TSE_0_LO 0x00000466
-
-#define REG_A6XX_RBBM_PERFCTR_TSE_0_HI 0x00000467
-
-#define REG_A6XX_RBBM_PERFCTR_TSE_1_LO 0x00000468
-
-#define REG_A6XX_RBBM_PERFCTR_TSE_1_HI 0x00000469
-
-#define REG_A6XX_RBBM_PERFCTR_TSE_2_LO 0x0000046a
-
#define REG_A6XX_RBBM_PERFCTR_TSE_2_HI 0x0000046b
#define REG_A6XX_RBBM_PERFCTR_TSE_3_LO 0x0000046c
#define REG_A6XX_GRAS_CNTL 0x00008005
#define A6XX_GRAS_CNTL_VARYING 0x00000001
-#define A6XX_GRAS_CNTL_UNK3 0x00000008
+#define A6XX_GRAS_CNTL_CENTROID 0x00000002
+#define A6XX_GRAS_CNTL_PERSAMP_VARYING 0x00000004
+#define A6XX_GRAS_CNTL_SIZE 0x00000008
+#define A6XX_GRAS_CNTL_SIZE_PERSAMP 0x00000020
#define A6XX_GRAS_CNTL_XCOORD 0x00000040
#define A6XX_GRAS_CNTL_YCOORD 0x00000080
#define A6XX_GRAS_CNTL_ZCOORD 0x00000100
#define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI 0x00008107
-#define REG_A6XX_GRAS_UNKNOWN_8109 0x00008109
+#define REG_A6XX_GRAS_SAMPLE_CNTL 0x00008109
+#define A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001
#define REG_A6XX_GRAS_UNKNOWN_8110 0x00008110
#define REG_A6XX_RB_RENDER_CONTROL0 0x00008809
#define A6XX_RB_RENDER_CONTROL0_VARYING 0x00000001
-#define A6XX_RB_RENDER_CONTROL0_UNK3 0x00000008
+#define A6XX_RB_RENDER_CONTROL0_CENTROID 0x00000002
+#define A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING 0x00000004
+#define A6XX_RB_RENDER_CONTROL0_SIZE 0x00000008
+#define A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP 0x00000020
#define A6XX_RB_RENDER_CONTROL0_XCOORD 0x00000040
#define A6XX_RB_RENDER_CONTROL0_YCOORD 0x00000080
#define A6XX_RB_RENDER_CONTROL0_ZCOORD 0x00000100
#define A6XX_RB_RENDER_CONTROL1_SAMPLEMASK 0x00000001
#define A6XX_RB_RENDER_CONTROL1_FACENESS 0x00000004
#define A6XX_RB_RENDER_CONTROL1_SAMPLEID 0x00000008
+#define A6XX_RB_RENDER_CONTROL1_UNK4 0x00000010
+#define A6XX_RB_RENDER_CONTROL1_UNK5 0x00000020
+#define A6XX_RB_RENDER_CONTROL1_SIZE 0x00000040
#define REG_A6XX_RB_FS_OUTPUT_CNTL0 0x0000880b
#define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z 0x00000002
+#define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK 0x00000004
#define REG_A6XX_RB_FS_OUTPUT_CNTL1 0x0000880c
#define A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f
#define A6XX_RB_SRGB_CNTL_SRGB_MRT6 0x00000040
#define A6XX_RB_SRGB_CNTL_SRGB_MRT7 0x00000080
-#define REG_A6XX_RB_UNKNOWN_8810 0x00008810
+#define REG_A6XX_RB_SAMPLE_CNTL 0x00008810
+#define A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001
#define REG_A6XX_RB_UNKNOWN_8811 0x00008811
#define REG_A6XX_RB_BLIT_FLAG_DST_HI 0x000088dd
+#define REG_A6XX_RB_BLIT_FLAG_DST_PITCH 0x000088de
+#define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK 0x000007ff
+#define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT 0
+static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(uint32_t val)
+{
+ assert(!(val & 0x3f));
+ return ((val >> 6) << A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK;
+}
+#define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK 0x003ff800
+#define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT 11
+static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(uint32_t val)
+{
+ assert(!(val & 0x7f));
+ return ((val >> 7) << A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK;
+}
+
#define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0 0x000088df
#define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1 0x000088e0
#define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_HI 0x00008901
#define REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x00008902
+#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff
+#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT 0
+static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
+{
+ assert(!(val & 0x3f));
+ return ((val >> 6) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK;
+}
+#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x003ff800
+#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11
+static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
+{
+ assert(!(val & 0x7f));
+ return ((val >> 7) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
+}
static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; }
#define REG_A6XX_RB_2D_DST_FLAGS_HI 0x00008c21
+#define REG_A6XX_RB_2D_DST_FLAGS_PITCH 0x00008c22
+#define A6XX_RB_2D_DST_FLAGS_PITCH_PITCH__MASK 0x000007ff
+#define A6XX_RB_2D_DST_FLAGS_PITCH_PITCH__SHIFT 0
+static inline uint32_t A6XX_RB_2D_DST_FLAGS_PITCH_PITCH(uint32_t val)
+{
+ assert(!(val & 0x3f));
+ return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PITCH_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PITCH_PITCH__MASK;
+}
+#define A6XX_RB_2D_DST_FLAGS_PITCH_ARRAY_PITCH__MASK 0x003ff800
+#define A6XX_RB_2D_DST_FLAGS_PITCH_ARRAY_PITCH__SHIFT 11
+static inline uint32_t A6XX_RB_2D_DST_FLAGS_PITCH_ARRAY_PITCH(uint32_t val)
+{
+ assert(!(val & 0x7f));
+ return ((val >> 7) << A6XX_RB_2D_DST_FLAGS_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PITCH_ARRAY_PITCH__MASK;
+}
+
#define REG_A6XX_RB_2D_SRC_SOLID_C0 0x00008c2c
#define REG_A6XX_RB_2D_SRC_SOLID_C1 0x00008c2d
return ((val) << A6XX_VPC_PACK_PSIZELOC__SHIFT) & A6XX_VPC_PACK_PSIZELOC__MASK;
}
+#define REG_A6XX_VPC_PACK_3 0x00009303
+#define A6XX_VPC_PACK_3_STRIDE_IN_VPC__MASK 0x000000ff
+#define A6XX_VPC_PACK_3_STRIDE_IN_VPC__SHIFT 0
+static inline uint32_t A6XX_VPC_PACK_3_STRIDE_IN_VPC(uint32_t val)
+{
+ return ((val) << A6XX_VPC_PACK_3_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_PACK_3_STRIDE_IN_VPC__MASK;
+}
+#define A6XX_VPC_PACK_3_NUMNONPOSVAR__MASK 0x0000ff00
+#define A6XX_VPC_PACK_3_NUMNONPOSVAR__SHIFT 8
+static inline uint32_t A6XX_VPC_PACK_3_NUMNONPOSVAR(uint32_t val)
+{
+ return ((val) << A6XX_VPC_PACK_3_NUMNONPOSVAR__SHIFT) & A6XX_VPC_PACK_3_NUMNONPOSVAR__MASK;
+}
+#define A6XX_VPC_PACK_3_PSIZELOC__MASK 0x00ff0000
+#define A6XX_VPC_PACK_3_PSIZELOC__SHIFT 16
+static inline uint32_t A6XX_VPC_PACK_3_PSIZELOC(uint32_t val)
+{
+ return ((val) << A6XX_VPC_PACK_3_PSIZELOC__SHIFT) & A6XX_VPC_PACK_3_PSIZELOC__MASK;
+}
+
#define REG_A6XX_VPC_CNTL_0 0x00009304
#define A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK 0x000000ff
#define A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT 0
#define REG_A6XX_VPC_UNKNOWN_9602 0x00009602
+#define REG_A6XX_PC_TESS_NUM_VERTEX 0x00009800
+
#define REG_A6XX_PC_UNKNOWN_9801 0x00009801
+#define REG_A6XX_PC_TESS_CNTL 0x00009802
+#define A6XX_PC_TESS_CNTL_SPACING__MASK 0x00000003
+#define A6XX_PC_TESS_CNTL_SPACING__SHIFT 0
+static inline uint32_t A6XX_PC_TESS_CNTL_SPACING(enum a6xx_tess_spacing val)
+{
+ return ((val) << A6XX_PC_TESS_CNTL_SPACING__SHIFT) & A6XX_PC_TESS_CNTL_SPACING__MASK;
+}
+#define A6XX_PC_TESS_CNTL_CCW 0x00000004
+#define A6XX_PC_TESS_CNTL_PRIMITIVES 0x00000008
+
#define REG_A6XX_PC_RESTART_INDEX 0x00009803
#define REG_A6XX_PC_MODE_CNTL 0x00009804
}
#define A6XX_PC_PRIMITIVE_CNTL_1_PSIZE 0x00000100
+#define REG_A6XX_PC_PRIMITIVE_CNTL_3 0x00009b03
+#define A6XX_PC_PRIMITIVE_CNTL_3_STRIDE_IN_VPC__MASK 0x0000007f
+#define A6XX_PC_PRIMITIVE_CNTL_3_STRIDE_IN_VPC__SHIFT 0
+static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_3_STRIDE_IN_VPC(uint32_t val)
+{
+ return ((val) << A6XX_PC_PRIMITIVE_CNTL_3_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_3_STRIDE_IN_VPC__MASK;
+}
+#define A6XX_PC_PRIMITIVE_CNTL_3_PSIZE 0x00000100
+
+#define REG_A6XX_PC_PRIMITIVE_CNTL_4 0x00009b04
+#define A6XX_PC_PRIMITIVE_CNTL_4_STRIDE_IN_VPC__MASK 0x0000007f
+#define A6XX_PC_PRIMITIVE_CNTL_4_STRIDE_IN_VPC__SHIFT 0
+static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_4_STRIDE_IN_VPC(uint32_t val)
+{
+ return ((val) << A6XX_PC_PRIMITIVE_CNTL_4_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_4_STRIDE_IN_VPC__MASK;
+}
+#define A6XX_PC_PRIMITIVE_CNTL_4_PSIZE 0x00000100
+
#define REG_A6XX_PC_UNKNOWN_9B06 0x00009b06
#define REG_A6XX_PC_UNKNOWN_9B07 0x00009b07
}
#define REG_A6XX_VFD_CONTROL_2 0x0000a002
-#define A6XX_VFD_CONTROL_2_REGID_PATCHID__MASK 0x000000ff
-#define A6XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT 0
-static inline uint32_t A6XX_VFD_CONTROL_2_REGID_PATCHID(uint32_t val)
+#define A6XX_VFD_CONTROL_2_REGID_HSPATCHID__MASK 0x000000ff
+#define A6XX_VFD_CONTROL_2_REGID_HSPATCHID__SHIFT 0
+static inline uint32_t A6XX_VFD_CONTROL_2_REGID_HSPATCHID(uint32_t val)
+{
+ return ((val) << A6XX_VFD_CONTROL_2_REGID_HSPATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_HSPATCHID__MASK;
+}
+#define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK 0x0000ff00
+#define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT 8
+static inline uint32_t A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(uint32_t val)
{
- return ((val) << A6XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_PATCHID__MASK;
+ return ((val) << A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK;
}
#define REG_A6XX_VFD_CONTROL_3 0x0000a003
-#define A6XX_VFD_CONTROL_3_REGID_PATCHID__MASK 0x0000ff00
-#define A6XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT 8
-static inline uint32_t A6XX_VFD_CONTROL_3_REGID_PATCHID(uint32_t val)
+#define A6XX_VFD_CONTROL_3_REGID_DSPATCHID__MASK 0x0000ff00
+#define A6XX_VFD_CONTROL_3_REGID_DSPATCHID__SHIFT 8
+static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSPATCHID(uint32_t val)
{
- return ((val) << A6XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_PATCHID__MASK;
+ return ((val) << A6XX_VFD_CONTROL_3_REGID_DSPATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSPATCHID__MASK;
}
#define A6XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000
#define A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16
#define REG_A6XX_SP_HS_UNKNOWN_A831 0x0000a831
+#define REG_A6XX_SP_HS_UNKNOWN_A833 0x0000a833
+
#define REG_A6XX_SP_HS_OBJ_START_LO 0x0000a834
#define REG_A6XX_SP_HS_OBJ_START_HI 0x0000a835
#define A6XX_SP_DS_CTRL_REG0_PIXLODENABLE 0x04000000
#define A6XX_SP_DS_CTRL_REG0_MERGEDREGS 0x80000000
+#define REG_A6XX_SP_DS_PRIMITIVE_CNTL 0x0000a842
+#define A6XX_SP_DS_PRIMITIVE_CNTL_DSOUT__MASK 0x0000001f
+#define A6XX_SP_DS_PRIMITIVE_CNTL_DSOUT__SHIFT 0
+static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_DSOUT(uint32_t val)
+{
+ return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_DSOUT__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_DSOUT__MASK;
+}
+
+static inline uint32_t REG_A6XX_SP_DS_OUT(uint32_t i0) { return 0x0000a843 + 0x1*i0; }
+
+static inline uint32_t REG_A6XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000a843 + 0x1*i0; }
+#define A6XX_SP_DS_OUT_REG_A_REGID__MASK 0x000000ff
+#define A6XX_SP_DS_OUT_REG_A_REGID__SHIFT 0
+static inline uint32_t A6XX_SP_DS_OUT_REG_A_REGID(uint32_t val)
+{
+ return ((val) << A6XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_A_REGID__MASK;
+}
+#define A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00000f00
+#define A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 8
+static inline uint32_t A6XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val)
+{
+ return ((val) << A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK;
+}
+#define A6XX_SP_DS_OUT_REG_B_REGID__MASK 0x00ff0000
+#define A6XX_SP_DS_OUT_REG_B_REGID__SHIFT 16
+static inline uint32_t A6XX_SP_DS_OUT_REG_B_REGID(uint32_t val)
+{
+ return ((val) << A6XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_B_REGID__MASK;
+}
+#define A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x0f000000
+#define A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 24
+static inline uint32_t A6XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val)
+{
+ return ((val) << A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK;
+}
+
+static inline uint32_t REG_A6XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000a853 + 0x1*i0; }
+
+static inline uint32_t REG_A6XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000a853 + 0x1*i0; }
+#define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
+#define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0
+static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val)
+{
+ return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK;
+}
+#define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
+#define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8
+static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val)
+{
+ return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK;
+}
+#define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
+#define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16
+static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val)
+{
+ return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK;
+}
+#define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
+#define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24
+static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val)
+{
+ return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK;
+}
+
+#define REG_A6XX_SP_DS_UNKNOWN_A85B 0x0000a85b
+
#define REG_A6XX_SP_DS_OBJ_START_LO 0x0000a85c
#define REG_A6XX_SP_DS_OBJ_START_HI 0x0000a85d
{
return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK;
}
+#define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK 0x00ff0000
+#define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT 16
+static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(uint32_t val)
+{
+ return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK;
+}
#define REG_A6XX_SP_FS_OUTPUT_CNTL1 0x0000a98d
#define A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f
#define REG_A6XX_SP_PS_2D_SRC_FLAGS_HI 0x0000b4cb
+#define REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH 0x0000b4cc
+#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__MASK 0x000007ff
+#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__SHIFT 0
+static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH(uint32_t val)
+{
+ assert(!(val & 0x3f));
+ return ((val >> 6) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__MASK;
+}
+#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__MASK 0x003ff800
+#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__SHIFT 11
+static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH(uint32_t val)
+{
+ assert(!(val & 0x7f));
+ return ((val >> 7) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__MASK;
+}
+
#define REG_A6XX_SP_UNKNOWN_B600 0x0000b600
#define REG_A6XX_SP_UNKNOWN_B605 0x0000b605
{
return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK;
}
+#define A6XX_HLSQ_CONTROL_2_REG_SIZE__MASK 0xff000000
+#define A6XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT 24
+static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SIZE(uint32_t val)
+{
+ return ((val) << A6XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SIZE__MASK;
+}
#define REG_A6XX_HLSQ_CONTROL_3_REG 0x0000b984
-#define A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK 0x000000ff
-#define A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT 0
-static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(uint32_t val)
+#define A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL__MASK 0x000000ff
+#define A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL__SHIFT 0
+static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(uint32_t val)
+{
+ return ((val) << A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL__MASK;
+}
+#define A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID__MASK 0x00ff0000
+#define A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID__SHIFT 16
+static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(uint32_t val)
{
- return ((val) << A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK;
+ return ((val) << A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID__MASK;
}
#define REG_A6XX_HLSQ_CONTROL_4_REG 0x0000b985
+#define A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP__MASK 0x000000ff
+#define A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP__SHIFT 0
+static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(uint32_t val)
+{
+ return ((val) << A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP__MASK;
+}
#define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000
#define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16
static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)
assert(!(val & 0xfff));
return ((val >> 12) << A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK;
}
-#define A6XX_TEX_CONST_3_FLAG 0x10000000
#define A6XX_TEX_CONST_3_UNK27 0x08000000
+#define A6XX_TEX_CONST_3_FLAG 0x10000000
#define REG_A6XX_TEX_CONST_4 0x00000004
#define A6XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0
}
#define REG_A6XX_TEX_CONST_9 0x00000009
-#define A6XX_TEX_CONST_9_FLAG_BUFFER_PITCH__MASK 0x0001ffff
-#define A6XX_TEX_CONST_9_FLAG_BUFFER_PITCH__SHIFT 0
-static inline uint32_t A6XX_TEX_CONST_9_FLAG_BUFFER_PITCH(uint32_t val)
+#define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK 0x0001ffff
+#define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0
+static inline uint32_t A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)
{
assert(!(val & 0xf));
- return ((val >> 4) << A6XX_TEX_CONST_9_FLAG_BUFFER_PITCH__SHIFT) & A6XX_TEX_CONST_9_FLAG_BUFFER_PITCH__MASK;
+ return ((val >> 4) << A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK;
}
#define REG_A6XX_TEX_CONST_10 0x0000000a
-#define A6XX_TEX_CONST_10_FLAG_BUFFER_ARRAY_PITCH__MASK 0x0001ffff
-#define A6XX_TEX_CONST_10_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0
-static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)
+#define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK 0x0000007f
+#define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT 0
+static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(uint32_t val)
{
assert(!(val & 0x3f));
- return ((val >> 6) << A6XX_TEX_CONST_10_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_ARRAY_PITCH__MASK;
+ return ((val >> 6) << A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK;
}
#define REG_A6XX_TEX_CONST_11 0x0000000b
assert(!(val & 0xfff));
return ((val >> 12) << A6XX_IBO_3_ARRAY_PITCH__SHIFT) & A6XX_IBO_3_ARRAY_PITCH__MASK;
}
+#define A6XX_IBO_3_UNK27 0x08000000
+#define A6XX_IBO_3_FLAG 0x10000000
#define REG_A6XX_IBO_4 0x00000004
#define A6XX_IBO_4_BASE_LO__MASK 0xffffffff
return ((val) << A6XX_IBO_5_DEPTH__SHIFT) & A6XX_IBO_5_DEPTH__MASK;
}
+#define REG_A6XX_IBO_6 0x00000006
+
+#define REG_A6XX_IBO_7 0x00000007
+
+#define REG_A6XX_IBO_8 0x00000008
+
+#define REG_A6XX_IBO_9 0x00000009
+#define A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__MASK 0x0001ffff
+#define A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0
+static inline uint32_t A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)
+{
+ assert(!(val & 0xf));
+ return ((val >> 4) << A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__MASK;
+}
+
+#define REG_A6XX_IBO_10 0x0000000a
+#define A6XX_IBO_10_FLAG_BUFFER_PITCH__MASK 0x0000007f
+#define A6XX_IBO_10_FLAG_BUFFER_PITCH__SHIFT 0
+static inline uint32_t A6XX_IBO_10_FLAG_BUFFER_PITCH(uint32_t val)
+{
+ assert(!(val & 0x3f));
+ return ((val >> 6) << A6XX_IBO_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_IBO_10_FLAG_BUFFER_PITCH__MASK;
+}
+
+#define REG_A6XX_UBO_0 0x00000000
+#define A6XX_UBO_0_BASE_LO__MASK 0xffffffff
+#define A6XX_UBO_0_BASE_LO__SHIFT 0
+static inline uint32_t A6XX_UBO_0_BASE_LO(uint32_t val)
+{
+ return ((val) << A6XX_UBO_0_BASE_LO__SHIFT) & A6XX_UBO_0_BASE_LO__MASK;
+}
+
+#define REG_A6XX_UBO_1 0x00000001
+#define A6XX_UBO_1_BASE_HI__MASK 0x0001ffff
+#define A6XX_UBO_1_BASE_HI__SHIFT 0
+static inline uint32_t A6XX_UBO_1_BASE_HI(uint32_t val)
+{
+ return ((val) << A6XX_UBO_1_BASE_HI__SHIFT) & A6XX_UBO_1_BASE_HI__MASK;
+}
+
+#define REG_CP_UNK_A6XX_55_0 0x00000000
+#define CP_UNK_A6XX_55_0_BASE_LO__MASK 0xffffffff
+#define CP_UNK_A6XX_55_0_BASE_LO__SHIFT 0
+static inline uint32_t CP_UNK_A6XX_55_0_BASE_LO(uint32_t val)
+{
+ return ((val) << CP_UNK_A6XX_55_0_BASE_LO__SHIFT) & CP_UNK_A6XX_55_0_BASE_LO__MASK;
+}
+
+#define REG_CP_UNK_A6XX_55_1 0x00000001
+#define CP_UNK_A6XX_55_1_BASE_HI__MASK 0x0001ffff
+#define CP_UNK_A6XX_55_1_BASE_HI__SHIFT 0
+static inline uint32_t CP_UNK_A6XX_55_1_BASE_HI(uint32_t val)
+{
+ return ((val) << CP_UNK_A6XX_55_1_BASE_HI__SHIFT) & CP_UNK_A6XX_55_1_BASE_HI__MASK;
+}
+
+#define REG_CP_UNK_A6XX_55_2 0x00000002
+#define CP_UNK_A6XX_55_2_SIZE__MASK 0x0000ffff
+#define CP_UNK_A6XX_55_2_SIZE__SHIFT 0
+static inline uint32_t CP_UNK_A6XX_55_2_SIZE(uint32_t val)
+{
+ return ((val) << CP_UNK_A6XX_55_2_SIZE__SHIFT) & CP_UNK_A6XX_55_2_SIZE__MASK;
+}
+
#define REG_A6XX_PDC_GPU_ENABLE_PDC 0x00001140
#define REG_A6XX_PDC_GPU_SEQ_START_ADDR 0x00001148
projects / mesa.git / blobdiff